2026-09-16
1 items 52 entities 79 connections
Processed 52 entities and 79 relations.
Cascade asymmetric ISA pre-simulation CPU fuzzing differential fuzzing program reduction coverage-guided fuzzing intermediate program construction control flow entanglement with data flow bug detection via program non-termination offset construction progressive memory allocation formal verification RTL simulation multiplexer select coverage control register coverage mutation-based test-case generation golden model comparison DifuzzRTL TheHuzz RFUZZ Spike Verilator Yosys HypFuzz RISC-V ISA Instruction Set Simulator (ISS) basic block cf-ambiguous instruction Control and Status Registers (CSRs) RTL design program completion rate prevalence of fuzzing instructions dependency chain privilege transition Floating-Point Unit (FPU) self-modifying code correct-by-construction programs fuzzing throughput register lifecycle state machine Cascade: CPU Fuzzing via Intricate Program Generation Flavien Solt Katharina Ceesay-Seitz Kaveh Razavi ETH Zurich USENIX VexRiscv PicoRV32 Kronos CVA6 Rocket core BOOM Cascade source code