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Control and Status Registers (CSRs)

Concept

Control and Status Registers (CSRs) are processor registers defined as part of an ISA that hold the control and status state of the processor. In the RISC-V architecture, CSRs are special-purpose registers specified by the privileged architecture that enable trap handling, environment interaction, performance monitoring, and identification. They include identification registers (marchid, mvendorid, mhartid), trap delegation registers (medeleg, mideleg), the Machine Interrupt Register (mip), machine and unprivileged performance counters (mcycle, minstret, mcycleh, minstreth, cycle, cycleh, instret, instreth, time, timeh), and setup/enable registers (mhpmcounter3-31, mhpmcounter3-31h, mhpmevent3-31, mscratch, mcounteren). The article covers CSR-specific architectural rules (including mandatory illegal instruction exceptions on writes to read-only CSRs and on accesses to non-existent CSRs), CSR-aware test generation, CSR transitions as a fuzzing coverage signal in ProcessorFuzz, and CSR mismatches and bugs identified via symbolic co-simulation of MicroRV32.

First seen 5/29/2026
Last seen 7/12/2026
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Definition

Control and Status Registers (CSRs) are processor registers defined as part of an ISA that hold the control and status state of the processor. In the RISC-V architecture, CSRs are special-purpose registers specified by the privileged architecture that enable trap handling, environment interaction, performance monitoring, and identification. The set of RISC-V CSRs discussed in this article includes:

  • Identification (read-only): marchid (Machine Architecture ID Register), mvendorid (Machine Vendor ID Register), and mhartid (Hart ID Register).
  • Trap delegation (read/write): medeleg (Machine Exception Delegation Register) and mideleg (Machine Interrupt Delegation Register).
  • Interrupts: mip (Machine Interrupt Register).
  • Machine-mode performance counters: mcycle, minstret, mcycleh, minstreth, and mhpmcounter3-31 / mhpmcounter3-31h.
  • Unprivileged counters: cycle, cycleh, instret, instreth, time, timeh.
  • Counter setup/enable: mhpmevent3-31 (Machine Counter Setup CSR), mscratch (Machine Scratch CSR), and mcounteren (Machine Counter-Enable Register).
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NEIGHBORHOOD

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RELATIONSHIPS

11 connections
RISC-V part of → 100% 5e
CSRs are defined in the RISC-V privileged architecture specification.
RISC-V Instruction Set Architecture part of → 95% 3e
CSRs are part of the RISC-V ISA, storing additional instruction results.
Processor Verification using Symbolic Execution: A RISC-V Case-Study ← uses 90% 2e
The paper handles CSR verification and notes riscv-formal does not support CSRs.
Functional test constraint derivation ← uses 90% 2e
Functional test constraint derivation uses CSR behavior as part of the specification.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← uses 95% 2e
The paper supports CSR instructions in its instruction stream generation.
Cascade ← uses 95% 1e
Cascade generates programs that operate under randomized CSRs
ISA Simulation part of → 90% 1e
CSRs are system registers in ISA specifications that track processor state.
Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← mentions 90% 1e
The paper mentions CSRs as instructions supported in its unrestricted instruction stream.
Endless Instruction Stream ← uses 90% 1e
Endless instruction streams include arbitrary CSR instructions without restrictions.
riscv-dv ← uses 85% 1e
RISC-V DV tracks changes to CSRs in its execution trace.
Software-Based Self-Test (SBST) ← uses 90% 1e
SBST test specifications include allowed CSR accesses and configurations.

LINKED ENTITIES

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RISC-V PART_OF Extracted graph relationship

CITATIONS

6 sources
6 citations — click to expand
[1] CSRs are system registers in an ISA specification that hold the architectural control and status state of the processor, and ProcessorFuzz compares CSR values between consecutive instructions in an ISA simulation to track CSR transitions for fuzzing feedback. ProcessorFuzz: Guiding Processor Fuzzing using Control and Status Registers
[2] In RISC-V, CSRs specified by the privileged architecture include identification registers (marchid, mvendorid, mhartid), trap delegation registers (medeleg, mideleg), the Machine Interrupt Register (mip), machine and unprivileged performance counters (mcycle, minstret, mcycleh, minstreth, cycle, cycleh, instret, instreth, time, timeh), and counter setup/enable registers (mhpmcounter3-31, mhpmcounter3-31h, mhpmevent3-31, mscratch, mcounteren). Processor Verification using Symbolic Execution - AGRA | Uni Bremen
[3] The RISC-V specification mandates that an illegal instruction exception be raised if a write attempt to a read-only CSR occurs (e.g., marchid, mvendorid, mhartid), and that an illegal instruction exception must be raised when a CSR instruction accesses non-existent CSRs. Processor Verification using Symbolic Execution - AGRA | Uni Bremen
[4] In the symbolic-execution + co-simulation case study on MicroRV32 and the open-source RISC-V VP ISS, the RTL core fails to raise the mandatory illegal instruction exceptions on writes to read-only CSRs and on accesses to non-existent CSRs; the ISS is erroneous because it raises a trap at every read attempt of medeleg and mideleg; and the RTL core raises a trap at every write access to mip, mcycle, minstret, mcycleh, and minstreth. Processor Verification using Symbolic Execution - AGRA | Uni Bremen
[5] Counter-value deviations between the RTL core and the ISS are classified as implementation mismatches rather than errors because the detailed counting behavior is not specified, and the ISS additionally implements unprivileged counters (cycle, cycleh, instret, instreth, time, timeh) and machine counters (mhpmcounter3-31, mhpmcounter3-31h) while the RTL core omits mhpmevent3-31, mscratch, and mcounteren. Processor Verification using Symbolic Execution - AGRA | Uni Bremen
[6] In injected-error experiments on E0–E9, the case study used assumptions that block the generation of CSR instructions (which are not part of RV32I) to filter the known CSR-related implementation mismatches. Processor Verification using Symbolic Execution - AGRA | Uni Bremen