Debug Mode

Concept

Debug Mode is a special execution state entered by a RISC-V core (such as Ibex) in response to external debug requests. Because instruction-set simulator (ISS) golden models cannot model traps caused by external stimulus, verifying Debug Mode entry and associated CSR updates in the Ibex end-to-end RTL/ISS co-simulation flow relies on a runtime handshaking mechanism provided by the RISCV-DV instruction generator. The handshake lets the running core report status information to the testbench during execution, with the Ibex testbench using the signature address `0x8ffffffc`. Trace comparison is adapted so that only the final register values at end of test are compared, since the ISS trace log does not contain execution information for code that runs in the debug ROM or interrupt handlers.

First seen 6/6/2026

Last seen 8/27/2026

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Overview

In the Ibex core verification flow, Debug Mode is a privileged execution state entered by the core when it receives an external debug request. Verifying correct entry into Debug Mode, and verifying that the appropriate Control and Status Registers (CSRs) are updated, is a distinct concern from normal instruction-level correctness checking.

The RISC-V Debug Specification exists precisely because hardware debug needs a common architecture across diverse implementations, and Debug Mode is the architectural vehicle by which a RISC-V core transitions into that debug-specific execution context.

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RELATIONSHIPS

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handshaking mechanism ← uses 1e

The handshaking mechanism is used to verify that the core has entered Debug Mode correctly.

RISC-V Debug Specification ← mentions 93% 1e

The Debug Specification provides a common architecture for hardware debug including debug mode.

EBreakDbg Instruction Category ← mentions 1e

EBreakDbg Instruction Category involves entering Debug Mode.

DRet Instruction Category ← mentions 1e

DRet Instruction Category involves returning from Debug Mode.

riscv-dv ← uses 1e

RISCV-DV supports debug mode.

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riscv-dv USES Extracted graph relationship

CITATIONS

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8 citations — click to expand

[1] Debug Mode is a special execution state of the Ibex core entered in response to external debug requests. Verification — Ibex Documentation

[2] ISS models can simulate traps due to exceptions but cannot model traps due to external stimulus, so the ISS trace log will not contain execution information for code in the debug ROM or interrupt handlers. Verification — Ibex Documentation

[3] The handshaking mechanism from the RISCV-DV instruction generator is used to verify Debug Mode entry and correct CSR updates, with the Ibex testbench using signature address 0x8ffffffc. Verification — Ibex Documentation

[4] API tasks in dv/uvm/core_ibex/tests/core_ibex_base_test.sv integrate the handshake into the Ibex test environment, and usage examples are in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv. Verification — Ibex Documentation

[5] Only the final register values at the end of the test are compared between the core and ISS trace logs, because debug ROM and trap-handler code do not appear in the ISS trace log. Verification — Ibex Documentation

[6] The Makefile dv/uvm/core_ibex/Makefile drives the end-to-end RTL/ISS co-simulation flow that exercises Debug Mode, and provides commands such as make, make OUT=, make TEST=, make VERBOSE=, make LSF_CMD=, make gen, make compile,rtl_sim, and make COV=1. Verification — Ibex Documentation

[7] RISCV-DV provides Debug Mode support with a fully randomized debug ROM. RISCV-DV Processor Verification

[8] The RISC-V Debug Specification exists because hardware debug needs a common architecture across diverse implementations, and many projects delay lockstep, trace, and Debug Mode validation until late in the schedule. RISC-V Verification: Five Places Projects Lose Weeks