Debug Mode

Concept

Debug Mode is a special execution state of the Ibex RISC-V core that is entered in response to external debug requests. Because ISS-based reference models cannot model traps caused by external stimulus, verifying that the core has properly entered Debug Mode and updated the relevant CSRs relies on a runtime handshaking mechanism that lets the core report status information to the testbench during program execution.

First seen 6/6/2026

Last seen 6/6/2026

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Overview

In the Ibex core verification flow, Debug Mode is a privileged execution state entered by the core when it receives an external debug request. Verifying correct entry into Debug Mode, and verifying that the appropriate Control and Status Registers (CSRs) are updated, is a distinct concern from normal instruction-level correctness checking.

Verification Challenge

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handshaking mechanism ← uses 1e

The handshaking mechanism is used to verify that the core has entered Debug Mode correctly.

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CITATIONS

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[1] Debug Mode is entered by the core in response to external debug requests, which are a form of external stimulus that ISS models cannot model as traps. Verification — Ibex Documentation

[2] The RISCV-DV handshaking mechanism is used to verify that the core has entered Debug Mode properly and updated any CSRs correctly, because it lets the core send status information to the testbench during program execution. Verification — Ibex Documentation

[3] The signature address used by the Ibex testbench for the handshaking mechanism is 0x8ffffffc. Verification — Ibex Documentation

[4] The ISS trace log does not contain any execution information in the debug ROM or in any interrupt handler code, so a modified trace comparison is used: only the final values of every register at the end of the test are compared. Verification — Ibex Documentation

[5] API tasks for the handshaking mechanism are provided in dv/uvm/core_ibex/tests/core_ibex_base_test.sv, and example usage in real simulations is in dv/uvm/core_ibex/tests/core_ibex_test_lib.sv. Verification — Ibex Documentation

[6] The end-to-end RTL/ISS co-simulation flow that exercises Debug Mode scenarios is controlled by the Makefile at dv/uvm/core_ibex/Makefile. Verification — Ibex Documentation