Liste der Publikationen im Scale4Edge Projekt der Universit¨at Bremen

Arbeitsgruppe Rechnerarchitektur, Universit¨at Bremen

Nachfolgend findet sich die Lister der relevanten Publikationen die im Rahmen des Scale4Edge
Projekts durch die Universit¨at Bremen (UHB) entstanden sind.

Publikationen [1] Sallar Ahmadi-Pour. From abstract systems to concrete chips: bridging gaps in abstraction techniques for design, verification and optimization with modern system-based hardware development. Dez. 2025. doi: 10.26092/elib/5344. url: https://media.suub.uni- bremen.de/handle/elib/23793. [2] Sallar Ahmadi-Pour, Muhammad Hassan und Rolf Drechsler. “Cross-Level Verification of Hardware Peripherals”. In: RISC-V Summit Europe 2024. RISC-V International. 2023. [3] Sallar Ahmadi-Pour, Vladimir Herdt und Rolf Drechsler. “Constrained random verification for RISC-V: overview, evaluation and discussion”. In: MBMV 2021; 24th Workshop. VDE. 2021, S. 1–8. [4] Sallar Ahmadi-Pour, Vladimir Herdt und Rolf Drechsler. “MicroRV32-A SpinalHDL based RV32I Implementation Suitable for FPGAs”. In: (2021). [5] Sallar Ahmadi-Pour, Vladimir Herdt und Rolf Drechsler. “MircoRV32: an open source RISC-V cross-level platform for education and research”. In: Proceedings of the Workshop on Design Automation for CPS and IoT. 2021, S. 30–35. [6] Sallar Ahmadi-Pour, Vladimir Herdt und Rolf Drechsler. “RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems”. In: 2021 Forum on specification & Design Languages (FDL). IEEE. 2021, S. 01–07. [7] Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler und Klaus McDonald- Maier. “Task mapping and scheduling in FPGA-based heterogeneous real-time systems: A RISC-V case-study”. In: 2022 25th Euromicro Conference on Digital System Design (DSD). IEEE. 2022, S. 134–141. [8] Niklas Bruns. “Virtual Prototype Centric Verification for Embedded System Development”. Diss. Universit¨at Bremen, 2023. [9] Niklas Bruns, Sallar Ahmadi-Pour, S¨oren Tempel und Rolf Drechsler. “Towards Compre- hensive Verification of Hardware and Software for RISC-V based Embedded Systems”. In: (2023). [10] Niklas Bruns, Vladimir Herdt und Rolf Drechsler. “Processor verification using symbolic execution: A RISC-V case-study”. In: 2023 Design, Automation & Test in Europe Confe- rence & Exhibition (DATE). IEEE. 2023, S. 1–6.

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[11] Niklas Bruns, Vladimir Herdt und Rolf Drechsler. “Unified hw/sw coverage: A novel metric to boost coverage-guided fuzzing for virtual prototype based hw/sw co-verification”. In: 2022 Forum on Specification & Design Languages (FDL). IEEE. 2022, S. 1–8. [12] Niklas Bruns, Vladimir Herdt, Daniel Große und Rolf Drechsler. “Efficient cross-level pro- cessor verification using coverage-guided fuzzing”. In: Proceedings of the Great Lakes Sym- posium on VLSI 2022. 2022, S. 97–103. [13] Niklas Bruns, Vladimir Herdt, Daniel Große und Rolf Drechsler. “Toward RISC-V CSR Compliance Testing”. In: IEEE Embedded Systems Letters 13.4 (2021), S. 202–205. [14] Niklas Bruns, Vladimir Herdt, Eyck Jentzsch und Rolf Drechsler. “Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging”. In: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE. 2022, S. 1123–1126. [15] Niklas Bruns, Vladimir Herdt, Eyck Jentzsch und Rolf Drechsler. “RISC-V Processor Ve- rification with Coverage-guided Aging”. In: MBMV 2022; 25. Workshop. VDE. 2022. [16] Ece Nur Demirhan Co¸skun, Sallar Ahmadi-Pour, Muhammad Hassan und Rolf Drechsler. “Security Coverage Metrics for Information Flow at the System Level”. In: 2024 29th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE. 2024, S. 945–950. [17] Ece Nur Demirhan Coskuna, Sallar Ahmadi-Pourb, Muhammad Hassana und Rolf Drechs- lera. “Towards Completeness: Security Coverage Metrics for System Level Information Flow”. In: MBMV 2024; 27. Workshop. VDE. 2024, S. 160–163. [18] Wolfgang Ecker, Milos Krstic, Andreas Mauderer, Eyck Jentzsch, Mihaela Damian, Julian Oppermann, Andreas Koch, Peer Adelt, Wolfgang M¨uller, Vladimir Herdt, Rolf Drechs- ler, Rafael Stahl, Karsten Emrich, Daniel M¨uller-Gritschneder, Jan Schlamelcher, Kim Gr¨uttner, J¨org Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wim- mer, Bernd Becker, Philipp Scholl, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch und Christian Mayr. “The Scale4Edge RISC-V ecosystem”. In: 2022 Design, Au- tomation & Test in Europe Conference & Exhibition (DATE). IEEE. 2022, S. 808–813. [19] Wolfgang Ecker, Milos Krstic, Markus Ulbricht, Andreas Mauderer, Eyck Jentzsch, An- dreas Koch, Bastian Koppelmann, Wolfgang Mueller, Babak Sadiye, Niklas Bruns, Rolf Drechsler, Daniel Mueller-Gritschneder, Jan Schlamelcher, Kim Gr¨uttner, J¨org Bormann, Wolfgang Kunz, Reinhold Heckmann, Gerhard Angst, Ralf Wimmer, Bernd Becker, Tobi- as Faller, Paul Palomero Bernardo, Oliver Bringmann, Johannes Partzsch und Christian Mayr. “Scale4Edge - Scaling RISC-V for Edge Applications”. In: RISC-V International. 2023. [20] Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt und Rolf Drechsler. “Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification”. In: 2023 Forum on Specification & Design Languages (FDL). IEEE. 2023, S. 1–8. [21] Muhammad Hassan, Mohamed Nadeem, Khushboo Qayyum, Chandan Kumar Jha und Rolf Drechsler. “Prompt. verify. repeat. llms in the hardware verification cycle”. In: 2025 IEEE International Conference on Omni-layer Intelligent Systems (COINS). IEEE. 2025, S. 1–6. [22] Vladimir Herdt und Rolf Drechsler. “Advanced virtual prototyping for cyber-physical sys- tems using RISC-V: implementation, verification and challenges”. In: Science China Infor- mation Sciences 65.1 (2022), S. 110201. [23] Vladimir Herdt, Daniel Große und Rolf Drechsler. “Enhanced Virtual Prototyping”. In: Cham: Springer (2020). [24] Vladimir Herdt, Daniel Große und Rolf Drechsler. “RVX-a tool for concolic testing of em- bedded binaries targeting RISC-V platforms”. In: International Symposium on Automated Technology for Verification and Analysis. Springer. 2020, S. 543–549.

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[25] Vladimir Herdt, Daniel Große, Eyck Jentzsch und Rolf Drechsler. “Efficient cross-level testing for processor verification: A RISC-V case-study”. In: 2020 Forum for Specification and Design Languages (FDL). IEEE. 2020, S. 1–7. [26] Vladimir Herdt, Daniel Große, Pascal Pieper und Rolf Drechsler. “RISC-V based virtual prototype: An extensible and configurable platform for the system-level”. In: Journal of Systems Architecture 109 (2020), S. 101756. [27] Vladimir Herdt, Daniel Große, S¨oren Tempel und Rolf Drechsler. “Adaptive simulation with virtual prototypes for RISC-V: switching between fast and accurate at runtime”. In: 2020 IEEE 38th International Conference on Computer Design (ICCD). IEEE. 2020, S. 312–315. [28] Vladimir Herdt, Daniel Große, S¨oren Tempel und Rolf Drechsler. “Adaptive simulation with virtual prototypes in an open-source RISC-V evaluation platform”. In: Journal of Systems Architecture 116 (2021), S. 102135. [29] Vladimir Herdt, Hoang M Le, Daniel Große und Rolf Drechsler. “Verifying SystemC using intermediate verification language and stateful symbolic simulation”. In: IEEE Transacti- ons on Computer-Aided Design of Integrated Circuits and Systems 38.7 (2018), S. 1359– 1372. [30] Vladimir Herdt, S¨oren Tempel, Daniel Große und Rolf Drechsler. “Mutation-based com- pliance testing for RISC-V”. In: Proceedings of the 26th Asia and South Pacific Design Automation Conference. 2021, S. 55–60. [31] Chandan Kumar Jha, Muhammad Hassan, Khushboo Qayyum, Sallar Ahmadi-Pour, Kang- wei Xu, Ruidi Qiu, Jason Blocklove, Luca Collini, Andre Nakkab, Ulf Schlichtmann, Grace Li Zhang, Ramesh Karri, Bing Li, Siddharth Garg und Rolf Drechsler. “Large Langua- ge Models (LLMs) for Verification, Testing, and Design”. In: 2025 IEEE European Test Symposium (ETS). IEEE. 2025, S. 1–10. [32] Sajjad Parvin, Sallar Ahmadi-Pour, Chandan Kumar Jha, Frank Sill Torres und Rolf Drechsler. “Lo-RISK: Design of a low optical leakage and high performance RISC-V co- re”. In: 2023 IEEE International Conference on Omni-layer Intelligent Systems (COINS). IEEE. 2023, S. 1–4. [33] Pascal Pieper. “Better Early Than Never: Formal and Practical Techniques for the Complex System Design Process Using Virtual Prototypes”. Diss. Universit¨at Bremen, 2023. [34] Pascal Pieper, Vladimir Herdt und Rolf Drechsler. “Advanced embedded system modeling and simulation in an open source RISC-V virtual prototype”. In: Journal of Low Power Electronics and Applications 12.4 (2022), S. 52. [35] Pascal Pieper, Vladimir Herdt, Daniel Große und Rolf Drechsler. “Dynamic information flow tracking for embedded binaries using SystemC-based virtual prototypes”. In: 2020 57th ACM/IEEE Design Automation Conference (DAC). IEEE. 2020, S. 1–6. [36] Pascal Pieper, Vladimir Herdt, Daniel Große und Rolf Drechsler. “Verifying SystemC TLM peripherals using modern C++ symbolic execution tools”. In: Proceedings of the 59th ACM/IEEE Design Automation Conference. 2022, S. 1177–1182. [37] Pascal Pieper, Ralf Wimmer, Gerhard Angst und Rolf Drechsler. “Minimally invasive HW/SW co-debug live visualization on architecture level”. In: Proceedings of the 2021 Great Lakes Symposium on VLSI. 2021, S. 321–326. [38] Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha und Rolf Drechsler. “From bugs to fixes: Hdl bug identification and patching using llms and rag”. In: 2024 IEEE LLM Aided Design Workshop (LAD). IEEE. 2024, S. 1–5.

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[39] Khushboo Qayyum, Muhammad Hassan, Sallar Ahmadi-Pour, Chandan Kumar Jha und Rolf Drechsler. “Late breaking results: LLM-assisted automated incremental proof genera- tion for hardware verification”. In: Proceedings of the 61st ACM/IEEE Design Automation Conference. 2024, S. 1–2. [40] Deepak Ravibabu, Sallar Ahmadi-Pour, Muhammad Hassan, Abhoy Kole, Chandan Kumar Jha und Rolf Drechsler. “System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit”. In: 2025 Forum on Specification & Design Languages (FDL). IEEE. 2025, S. 1–9. [41] Deepak Ravibabu, Muhammad Hassan, Thilo V¨ortler, Karsten Einwich, Rolf Drechsler und Daniel Große. “Towards Non-Intrusive SystemC Checkpointing for Digital Virtual Prototypes”. In: MBMV 2025; 28. Workshop. VDE. 2025, S. 41–51. [42] Frank Riese, Vladimir Herdt, Daniel Große und Rolf Drechsler. “Metamorphic testing for processor verification: A RISC-V case study at the instruction level”. In: 2021 IFIP/IEEE 29th International Conference on Very Large Scale Integration (VLSI-SoC). IEEE. 2021, S. 1–6. [43] Karl Aaron Rudkowski, Sallar Ahmadi-Pour und Rolf Drechsler. “Comparing Methods for the Cross-Level Verification of SystemC Peripherals with Symbolic Execution”. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2025), S. 1–1. doi: 10.1109/TCAD.2025.3641038. [44] Karl Aaron Rudkowski, Sallar Ahmadi-Pour und Rolf Drechsler. “CrosSym: Cross-Level Verification of SystemC Peripherals using Symbolic Execution”. In: 2025 IEEE 28th In- ternational Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE. 2025, S. 153–156. [45] Karl Aaron Rudkowski, Sallar Ahmadi-Pour und Rolf Drechsler. “Symbolic Execution of Unmodified SystemC Peripherals”. In: MBMV 2025; 28. Workshop. VDE. 2025. [46] Muhammad Hassan Sallar Ahmadi-Pour und Rolf Drechsler. “Expanding RISC-V Horiz- ons: Streamlining Heterogeneous Systems Evaluation with Open Source RISC-V AMS VP Framework”. In: RISC-V Summit Europe 2023. RISC-V International. 2023. [47] S¨oren Tempel. Accurate binary-level symbolic execution of embedded firmware. Juni 2024. doi: 10.26092/elib/3090. url: https://media.suub.uni-bremen.de/handle/elib/ 8056. [48] S¨oren Tempel, Tobias Brandt und Christoph L¨uth. “Versatile and flexible modelling of the RISC-V instruction set architecture”. In: International Symposium on Trends in Functional Programming. Springer. 2023, S. 16–35. [49] S¨oren Tempel, Tobias Brandt, Christoph L¨uth, Christian Dietrich und Rolf Drechsler. “Accurate and Extensible Symbolic Execution of Binary Code based on Formal ISA Se- mantics”. In: 2025 Design, Automation & Test in Europe Conference (DATE). IEEE. 2025, S. 1–7. [50] S¨oren Tempel, Tobias Brandt, Christoph L¨uth und Rolf Drechsler. “Minimally invasive generation of RISC-V instruction set simulators from formal ISA models”. In: 2023 Forum on Specification & Design Languages (FDL). IEEE. 2023, S. 1–8. [51] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “An effective methodology for integra- ting Concolic testing with SystemC-based virtual prototypes”. In: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE. 2021, S. 218–221. [52] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “Automated detection of spatial memo- ry safety violations for constrained devices”. In: 2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC). IEEE. 2022, S. 160–165.

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[53] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “SISL: Concolic testing of structured binary input formats via partial specification”. In: International Symposium on Automated Technology for Verification and Analysis. Springer. 2022, S. 77–82. [54] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “Specification-based symbolic execution for stateful network protocol implementations in iot”. In: IEEE Internet of Things Journal 10.11 (2023), S. 9544–9555. [55] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “SymEx-VP: An open source virtu- al prototype for OS-agnostic concolic testing of IoT firmware”. In: Journal of Systems Architecture 126 (2022), S. 102456. [56] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “Towards Quantification and Visua- lization of the Effects of Concretization During Concolic Testing”. In: IEEE Embedded Systems Letters 14.4 (2022), S. 195–198. [57] S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “Towards reliable spatial memory safety for embedded software by combining checked C with Concolic testing”. In: 2021 58th ACM/IEEE Design Automation Conference (DAC). IEEE. 2021, S. 667–672. [58] Weiyan Zhang, Mehran Goli, Muhammad Hassan und Rolf Drechsler. “Efficient ML-based performance estimation approach across different microarchitectures for RISC-V proces- sors”. In: 2023 26th Euromicro Conference on Digital System Design (DSD). IEEE. 2023, S. 693–699. [59] Weiyan Zhang, Muhammad Hassan und Rolf Drechsler. “LLM-assisted Methodology for Embedded Software Performance Estimation on RISC-V”. In: RISC-V Summit Europe 2025. RISC-V International. 2025. [60] Weiyan Zhang, Muhammad Hassan und Rolf Drechsler. “LLM-assisted Performance Esti- mation of Embedded Software on RISC-V Processors”. In: 2025 IEEE 28th International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS). IEEE. 2025, S. 7–12. [61] Jan Zielasko, S¨oren Tempel, Vladimir Herdt und Rolf Drechsler. “3D visualization of sym- bolic execution traces”. In: 2022 Forum on Specification & Design Languages (FDL). IEEE. 2022, S. 1–8.

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