MIPS
ISAMIPS is an ISA/processor-architecture target represented in the evidence by MIPS programs, emulation and concolic analysis tooling, pipelined processor implementations, and verification-oriented SystemVerilog hardware projects.
First seen 5/25/2026
Last seen 5/25/2026
Evidence 1 chunks
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MIPS
MIPS is treated here as an instruction-set architecture (ISA) and processor-architecture target. The provided evidence shows MIPS being used in three technical contexts: program analysis of MIPS assembly programs, encrypted/pipelined MIPS processor design, and a SystemVerilog implementation of a 5-stage pipelined MIPS CPU with verification infrastructure.[1][2][3]
Program analysis context
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6 sources6 citations — click to expand
[1] mips-program-analysis: MIPS programs are discussed as assembly-level programs whose equivalence or disequivalence can be analyzed. Tamarin: Concolic Disequivalence for MIPS
[2] tamarin-tooling: Tamarin uses alternating concolic execution for MIPS disequivalence and includes a MIPS emulator, symbolic trace recording, a concolic execution engine, and Z3 integration. Tamarin: Concolic Disequivalence for MIPS
[3] encrypted-mips-design: A public design describes a 32-bit encrypted MIPS processor based on MIPS pipeline architecture. Efficient Hardware Design and Implementation of Encrypted MIPS Processor
[4] encrypted-mips-instructions: The encrypted MIPS processor design includes DES encryption/decryption blocks, adds LKLW, LKUW, and CRYPT instructions, and reports 218 MHz synthesis-level and 744 MHz simulation-level operation. Efficient Hardware Design and Implementation of Encrypted MIPS Processor
[5] mips-cpu-repo: The Peggy-Gits/MIPS-CPU repository describes a 5-stage pipelined MIPS processor implemented with SystemVerilog and capable of hazard handling. Peggy-Gits/MIPS-CPU
[6] mips-cpu-verification: The Peggy-Gits/MIPS-CPU repository includes a UVM verification testbench with a randomizing instruction generator, monitor, and coverage collector. Peggy-Gits/MIPS-CPU