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2,519 chars| Loading | @@ -177,6 +177,39 @@ cv32-firmware: comp $(FIRMWARE)/firmware.hex | |
# +UVM_TESTNAME=uvmt_cv32_firmware_test_c \ |
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# +firmware=$(FIRMWARE)/firmware_unit_test.hex |
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############################################################################### |
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# Use Google instruction stream generator (RISCV-DV) to create new test-programs |
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comp_riscv-dv: |
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$(XRUN) $(XRUN_COMP_FLAGS) \ |
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$(XRUN_USER_COMPILE_ARGS) \ |
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-elaborate \ |
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+incdir+$(RISCVDV_PKG)/target/rv32imc \ |
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+incdir+$(RISCVDV_PKG)/user_extension \ |
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+incdir+$(RISCVDV_PKG)/tests \ |
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+incdir+$(COREVDV_PKG) \ |
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-f $(COREVDV_PKG)/manifest.f \ |
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-l $(COREVDV_PKG)/out_$(DATE)/run/compile.log |
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gen_riscv-dv: |
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$(XRUN) $(XRUN_RUN_FLAGS) \ |
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-xceligen rand_struct \ |
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+UVM_TESTNAME=corev_instr_base_test \ |
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+num_of_tests=2 \ |
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+start_idx=0 \ |
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+asm_file_name=$(CORE_TEST_DIR)/google-riscv-dv \ |
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-l $(COREVDV_PKG)/out_$(DATE)/sim_riscv_arithmetic_basic_test_0.log \ |
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+instr_cnt=10000 \ |
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+num_of_sub_program=0 \ |
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+directed_instr_0=riscv_int_numeric_corner_stream,4 \ |
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+no_fence=1 \ |
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+no_data_page=1 \ |
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+no_branch_jump=1 \ |
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+boot_mode=m \ |
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+no_csr_instr=1 |
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mv *.S $(CORE_TEST_DIR)/custom |
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corev-dv: clean_riscv-dv clone_riscv-dv comp_riscv-dv gen_riscv-dv |
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############################################################################### |
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# Clean up your mess! |
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| Loading | @@ -195,6 +228,6 @@ clean_eclipse: | |
rm -rf workspace |
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# All generated files plus the clone of the RTL |
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clean_all: clean clean_eclipse clean_core_tests clean_riscvdv clean_test_programs |
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clean_all: clean clean_eclipse clean_core_tests clean_riscv-dv clean_test_programs |
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rm -rf $(CV32E40P_PKG) |
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