APUOP Common Definition File

Concept

A shared C-macro-based definition file that centrally encodes SPU instruction metadata (identifier, format, opcode, mnemonic, assembler format, register-usage map, and pipeline kind) under the APUOP macro. It serves as a single source of instruction descriptions consumed by multiple tools built on top of the SPU reference model.

First seen 8/18/2026

Last seen 8/18/2026

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WIKI

Overview

The APUOP Common Definition File is a centralized, C-macro-based specification that defines the non-functional attributes of every Synergistic Processor Unit (SPU) instruction. It is consumed alongside the SPU Reference Model by multiple downstream tools, eliminating duplicated hand-written descriptions of the instruction set across those applications.

Macro Structure

Each instruction (other than its functional behavior) is declared in the common definition file using the APUOP C macro. A representative example for the add instruction is:

APUOP(M_A, RR, 0x0c0, "a", ASM_RR, 00112, FX2)
/* Add RT<-RA+RB */

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RELATIONSHIPS

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SPU Reference Model ← uses 100% 1e

The SPU reference model uses the APUOP common definition file alongside other applications such as the assembler and pipeline simulator.

Assembler ← uses 100% 1e

The assembler uses the APUOP common definition file to define instructions.

Pipeline Simulator ← uses 100% 1e

The pipeline simulator uses the APUOP common definition file for pipeline configuration.

LINKED ENTITIES

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SPU Reference Model USES Extracted graph relationship

Assembler USES Extracted graph relationship

Pipeline Simulator USES Extracted graph relationship

CITATIONS

6 sources

6 citations — click to expand

[1] Each SPU instruction's non-functional definition is declared with the APUOP C macro in a common definition file. An SPU Reference Model for Simulation, Random Test Generation and Verification

[2] The macro takes the instruction identifier, instruction format, opcode, mnemonic, assembler format, register-file usage, and pipeline kind as arguments. An SPU Reference Model for Simulation, Random Test Generation and Verification

[3] The reference model itself does not use all the information in the macro; other applications such as the assembler, pipeline simulator, logic RTL, and verification environment also reference it, and each item is used by at least one application. An SPU Reference Model for Simulation, Random Test Generation and Verification

[4] The 6th argument is a five-digit code, with the most significant digit always 0, followed by digits for RC, RB, RA, and RT; 0 = unused, 1 = source, 2 = target, 3 = source and target. An SPU Reference Model for Simulation, Random Test Generation and Verification

[5] A script converts the macro description into the RTL description used by register-dependency checking logic. An SPU Reference Model for Simulation, Random Test Generation and Verification

[6] In the instruction simulator configuration, the assembler and reference model both refer to the common definition file, so only the common definition file must be changed for instruction-set changes. An SPU Reference Model for Simulation, Random Test Generation and Verification