Overview
The APUOP Common Definition File is a centralized, C-macro-based specification that defines the non-functional attributes of every Synergistic Processor Unit (SPU) instruction. It is consumed alongside the SPU Reference Model by multiple downstream tools, eliminating duplicated hand-written descriptions of the instruction set across those applications.
Macro Structure
Each instruction (other than its functional behavior) is declared in the common definition file using the APUOP C macro. A representative example for the add instruction is:
APUOP(M_A, RR, 0x0c0, "a", ASM_RR, 00112, FX2)
/* Add RT<-RA+RB */
The macro arguments are interpreted as follows:
| Position | Meaning |
|---|---|
| 1st | Instruction identifier (e.g., M_A) |
| 2nd | Instruction format |
| 3rd | Opcode (e.g., 0x0c0) |
| 4th | Mnemonic (e.g., "a") |
| 5th | Assembler format (e.g., ASM_RR) |
| 6th | Register-file usage map (5-digit code) |
| 7th | Kind of pipeline used to execute the instruction |
Every argument is required by at least one downstream application; the SPU reference model itself does not need all of them.
Register-Usage Encoding (6th Argument)
The 6th macro argument encodes which registers are read, written, or both for an instruction. Up to four registers may participate, named RA, RB, RC, and RT.
From the most significant digit, the five digits represent:
- Always
0(reserved). RCregister usage.RBregister usage.RAregister usage.RTregister usage.
Digit values:
0— register is not used by the instruction.1— register is used as a source.2— register is used as a target.3— register is used both as a source and as a target.
For example, the add instruction "a" reads RA and RB as source registers and writes the sum into target RT, yielding the encoding 00112.
Usage Across Applications
A primary benefit of the common definition file is that adding or modifying an instruction typically requires editing only this one file. Downstream tools that read the macro include:
- SPU Reference Model — used for instruction-level simulation.
- Assembler — used to translate mnemonics into object code.
- Pipeline Simulator — used for timing/pipeline modeling.
- Logic RTL — a script converts the macro description (notably the register-usage field) into HDL register-dependency-checking logic.
- Verification environment — shares the same macro to keep functional and implementation views consistent.
Because every field of the APUOP macro is used by at least one consumer, the file acts as the single authoritative instruction-description source for the SPU toolchain.
Example: Instruction Simulator
In the SPU instruction simulator, the assembler and reference model both refer to the common definition file. Only the common file needs to be changed when an instruction is added or modified. The simulator reads a COFF file emitted by the assembler and loads memory contents and the program counter into the SPU-architected memory/register structures before executing instructions.