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STIMSMITH

Post-simulation Trace File Compare

Technique
First seen 8/14/2026
Last seen 8/14/2026
Evidence 3 chunks

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RELATIONSHIPS

7 connections
Instruction Stream Generator uses → 90% 2e
Post-simulation trace file compare uses an instruction stream generator to create test programs
Instruction Set Simulator uses → 95% 2e
Post-simulation trace file compare uses an ISS to generate a reference trace
GCC uses → 88% 1e
GCC is used to compile test programs for post-simulation trace file compare
LLVM uses → 88% 1e
LLVM is used to compile test programs for post-simulation trace file compare
Hybrid Verification Methodology ← uses 90% 1e
Hybrid methodology uses post-simulation trace file compare for ISA/unprivileged tests
RTL Simulation uses → 90% 1e
Post-simulation trace file compare requires RTL simulation to generate the DUT trace
RISC-V Design Verification part of → 95% 1e
Post-simulation trace file compare is one of the core techniques used in RISC-V design verification