assertions

Concept

Assertions are statements in verification contexts that express properties expected to hold during execution, simulation, or formal proof. They are used in hardware verification (as SystemVerilog Assertions and as scoreboard/checking components within UVM testbenches) for functional validation, debug observability, and coverage, in security monitoring of System-on-Chip designs, and in deductive software verification where tools such as Dafny rely on helper assertions as proof steps, with recent research exploring automated inference of those helper assertions.

First seen 5/28/2026

Last seen 6/21/2026

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WIKI

Overview

Assertions are statements used in verification to express properties that should hold during execution, simulation, or proof. Public evidence describes assertions as widely used for functional validation and coverage analysis in both software and hardware designs, where they support runtime error detection and faster error localization ^[1]. They can also be specialized for security monitoring, such as System-on-Chip vulnerability checks [public_context: arxiv 2001.06719]. In deductive software verification, assertions serve as helper proof steps that guide a verifier such as Dafny [public_context: arxiv 2511.00125].

Definition and role in verification methods

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formal verification ← uses 93% 1e

Formal verification requires adding assertions about design behavior that need to be verified.

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formal verification USES Extracted graph relationship

CITATIONS

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[1] Assertions are statements used in verification to express properties that should hold during execution, simulation, or proof, and are widely used for functional validation and coverage analysis. UVM based design verification of a RISC-V CPU core

[2] An assertion is defined as a statement about the design behavior that needs to be verified, used within functional, formal, and coverage-based verification methods. Survey of Verification of RISC-V Processors

[3] Verification test plans implement checks as scoreboards, interface or embedded assertions inside RTL or verification components. UVM based design verification of a RISC-V CPU core

[4] A UVM SystemVerilog testbench includes stimulus generator, driver, monitor, scoreboard, assertions for debug ability/observability, and coverage. Survey of Verification of RISC-V Processors

[5] SystemVerilog extends Verilog with assertions and randomization; SystemVerilog Assertion (SVA) is the dedicated assertion specification subset, with similarities to Property Specification Language. UVM based design verification of a RISC-V CPU core

[6] Security assertions have been used to monitor System-on-Chip vulnerabilities and detected all inserted vulnerabilities where functional assertions missed most. System-on-Chip Security Assertions

[7] The Dafny verifier often requires manual helper assertions; DAISY verifies 63.4% of programs with one missing assertion and 31.7% with multiple missing assertions, and programs can sometimes be verified with fewer assertions than originally present. Inferring multiple helper Dafny assertions with LLMs