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assertions

Concept WIKI v1 · 5/28/2026

Assertions are verification statements used to check expected properties, support coverage-oriented validation, detect errors at runtime, and localize failures. In hardware verification, they can be embedded in RTL, interfaces, or verification components and are supported by SystemVerilog Assertion. In formal software verification, helper assertions can guide tools such as Dafny, though inferring them automatically remains an active research topic.

Overview

Assertions are statements used in verification to express properties that should hold during execution, simulation, or proof. Public evidence describes assertions as widely used for functional validation and coverage analysis in both software and hardware designs, where they support runtime error detection and faster error localization. They can also be specialized for security monitoring, such as System-on-Chip vulnerability checks.

Role in hardware verification

In hardware verification planning, assertions are one possible checking mechanism alongside scoreboards. The RISC-V CPU verification evidence states that checking mechanisms for functional correctness should be captured in the verification test plan, and that checks can be implemented as scoreboards, interface assertions, or embedded assertions inside RTL or verification components.

SystemVerilog includes assertions as part of its verification-oriented feature set. The evidence describes SystemVerilog as extending Verilog with features for design, verification, and testbench development, including assertions and randomization for testbench stimulus. It also states that assertions help verify design properties that arise after particular conditions or states. SystemVerilog has a dedicated assertion specification subset, commonly called SystemVerilog Assertion, or SVA, with similarities to Property Specification Language.

Security assertions

Assertions can be used beyond ordinary functional checks. The public SoC-security source states that assertions have been used to monitor common System-on-Chip security vulnerabilities. In that work, security assertion classes enabled runtime checking of vulnerabilities, and the generated security assertions detected all inserted vulnerabilities in the reported experiments, while functional assertions generated by existing assertion-generation techniques missed most of them.

Helper assertions in formal verification

In deductive software verification, assertions may serve as helper proof steps. The public Dafny source reports that the Dafny verifier provides strong correctness guarantees but often requires many manual helper assertions, which can hinder adoption. The same source introduces DAISY, an LLM-based Dafny Assertion Inference System, and reports verification rates of 63.4% for programs with one missing assertion and 31.7% for programs with multiple missing assertions. It also observes that programs can sometimes be verified with fewer assertions than originally present, meaning that recovering every original assertion is not always necessary.

Practical implications

Across the cited contexts, assertions function as compact, executable or provable statements of expected behavior. They are useful when a verification plan must define both what is being checked and how it is checked. In simulation-based hardware verification, they can complement scoreboards and coverage-driven stimulus. In formal verification, they can encode intermediate facts that help a verifier complete a proof.

LINKED ENTITIES

2 links
UVM Based Design Verification of a RISC-V CPU Core USES
SystemVerilog FEATURE_OF

CITATIONS

6 sources
6 citations
[1] Assertions are widely used for functional validation and coverage analysis in both software and hardware designs, and they support runtime error detection and faster localization of errors. System-on-Chip Security Assertions
[2] Security-focused assertions can monitor System-on-Chip vulnerabilities; in the cited experiments, generated security assertions detected all inserted vulnerabilities while functional assertions generated by existing techniques missed most of them. System-on-Chip Security Assertions
[3] In a RISC-V CPU verification plan, checking mechanisms for functional correctness should be documented, and checks can be implemented as scoreboards, interface assertions, or embedded assertions inside RTL or verification components. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[4] SystemVerilog extends Verilog with verification and testbench features including assertions and randomization, and assertions help verify design properties that follow particular conditions or states. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[5] SystemVerilog has a dedicated assertion specification subset commonly referred to as SystemVerilog Assertion, or SVA, and it is described as similar to Property Specification Language. [PDF] UVM based design verification of a RISC-V CPU core - POLITesi
[6] The Dafny verifier often requires manual helper assertions; the DAISY system inferred missing assertions and verified 63.4% of programs with one missing assertion and 31.7% with multiple missing assertions. Inferring multiple helper Dafny assertions with LLMs