2026-08-17
1 items 44 entities 62 connections
Processed 44 entities and 62 relations.
LLM-based Processor Verification: A Case Study for Neuromorphic Processor simulation-based verification random test generation constrained random generation coverage-directed test generation coverage-directed test selection LLM-based test generation RAVEN RISCV-DV GPT-3.5 GPT-4 large language model domain specific architecture neuromorphic processor neuromorphic instruction set RISC-V Xuantie-C910 RTL simulation code coverage block coverage expression coverage toggle coverage ISA coverage prompt engineering hardware-aware test generation assembly test generation C program test generation novelty-driven verification Codex DAVE Chip-Chat ChipGPT design under test iterative test refinement functional verification branch prediction TrueNorth ISA extension method National University of Defense Technology University of Electronic Science and Technology of China Defense Innovation Institute Chao Xiao Lei Wang LLM-based verification workflow