2026-08-16
4 items 158 entities 211 connections
Processed 33 entities and 39 relations.
stimulus generator testbench test sequence generation cycle-accurate formal specification control flow graph Hoare triple generalized FSM model FSM traversal multistimulus execution channel microoperation stage driver stage monitor mediator response checker coverage tracker parallel-pipeline design semi-formal verification functional coverage interlock coverage multistimulus coverage precondition postcondition RTL model CTESK SeC Institute for System Programming of the Russian Academy of Sciences Mikhail Chupilko Alexander Kamkin MIPS64-compatible microprocessor L2 cache model checking simulation-based verification
Processed 76 entities and 98 relations.
Prelude Priming-Guided State Reconstruction Snapshot-Based Debugging Visibility Warm-Up Differential Testing Cycle-Accurate Replay Memory Footprint Analysis Scan-Chain-Based State Capture State Readback RTL Simulation FPGA-Based Prototyping Full-State Capture Micro-Architectural State Reconstruction Signal Tracing DESSERT ENCORE StateMover STATE-ACCESS VCS Verilator ILA SignalTap ChipScope Spike Xilinx Vivado BOOM Rocket RISC-V Out-of-Order Execution Architectural Registers Micro-Architectural State Pipeline Reorder Buffer (ROB) Branch Predictor Load-Store Queue (LSQ) Cache Hierarchy ISA Simulator RTL Signal Visibility Physical Register File DPI-C Interface PCIe Interface Data Extract Unit (DEU) Architectural Register Management Unit (AMU) Memory Rebuild Unit (MRU) AMD Virtex UltraScale+ VU19P FPGA CoreMark Embench Memory Footprint Instruction Set Architecture (ISA) Jialin Sun Yuchen Hu Dean You Zhe Jiang Xinwei Fang Southeast University University of York National Center of Technology Innovation for EDA Prelude: Priming-Guided State Reconstruction for Efficient FPGA Processor Debugging RISC-V DV ProcessorFuzz HyPFuzz Processor Fuzzing Instruction Fetch Unit (IFU) Program Counter (PC) General Purpose Registers (GPRs) Floating Point Registers (FPRs) Control and Status Registers (CSRs) UVLLM ISAAC MEIC RISCVuzz DiffTest-H Superscalar Processor Waveform Tracing Reproduction Rate
Processed 8 entities and 7 relations.
Processed 41 entities and 67 relations.
Specification-Based Test Program Generation for MIPS64 Memory Management Units A.S. Kamkin A.M. Kotsynyak Institute for System Programming of the Russian Academy of Sciences MicroTESK test program generation memory management unit MIPS64 MMUSL Genesys-Pro DeepTrans address translation translation lookaside buffer cache memory symbolic execution constraint solving formal specification test template instruction set architecture nML directed acyclic graph execution path combinatorial test generation page table Ruby Z3 SMT solver CVC4 SMT solver Fortress library MA2TG random test generation domain-specific language instruction set simulator memory segment microprocessor verification test data generation IBM D. Vorobyev A. Tatarnikov buffer-event factorization preparator MicroTESK