BOOM Core
ConceptBOOM Core is an open-source, out-of-order RISC-V processor core written in Chisel, used in academic research as a benchmark design-under-test (DUT) for hardware fuzzing, side-channel/leakage-contract verification, and hardware-security prototyping such as pointer encryption.
First seen 5/24/2026
Last seen 7/10/2026
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BOOM Core
BOOM Core is an open-source, out-of-order RISC-V processor core implemented in Chisel. It is part of the Rocket Chip ecosystem and is widely adopted in academic research as a complex out-of-order design-under-test (DUT) for hardware verification, security analysis, and prototyping of microarchitectural defenses.[1]
Role in hardware-fuzzing research
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2 connectionsHiFuzz is evaluated on the BOOM Core as one of three RISC-V targets.
ProcessorFuzz was evaluated on the BOOM core
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[1] BOOM Core is an open-source, out-of-order RISC-V Chisel core used as a DUT. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
[2] HiFuzz is implemented on Cocotb/Verilator/Spike with a Rainbow DQN Program Agent and a PPO Basic Block Agent, and is evaluated on Rocket, BOOM, and CVA6. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
[3] On the Encarsia benchmark, HiFuzz detects 18/30 bugs on BOOM versus 15/30 for each of DifuzzRTL, ProcessorFuzz, and Cascade, with the BOOM advantage attributed to stress on microarchitectural structures such as issue queues, buffers, and reorder buffers. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
[4] MUX coverage gains for HiFuzz over baselines are small on Rocket but widen substantially on the more complex out-of-order BOOM core, with the largest gains in hard-to-reach modules such as the FPU. HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing
[5] A 2025 coverage-guided pre-silicon fuzzing study evaluated BOOM together with Rocket and reported that increased microarchitectural coverage led to faster discovery of information-leakage vulnerabilities in the BOOM core. Coverage-Guided Pre-Silicon Fuzzing of Open-Source Processors based on Leakage Contracts
[6] LIPPEN was prototyped on FPGA using 64-bit RISC-V Rocket and BOOM cores, evaluated with microbenchmarks, nbench, and SPEC CPU2017, demonstrating comprehensive pointer protection with runtime overhead comparable to PAC and negligible area/power overhead. LIPPEN: A Lightweight In-Place Pointer Encryption Architecture for Pointer Integrity