Address translation
ConceptAddress translation is a hardware mechanism that maps addresses between different address spaces. In conventional CPUs it converts data virtual addresses into physical addresses using page tables accelerated by TLBs, and it can also be expressed as PC-indexed translation that uses a load instruction's PC to obtain a page table entry. In distributed multi-GPU scale-up systems, a destination-side variant called reverse address translation maps Network Physical Addresses (NPAs) to System Physical Addresses (SPAs) using Link MMUs and Link TLBs. Because the mechanism is highly complex, verification uses specification-based test program generation; IBM's DeepTrans/Genesys-Pro approach models translation as a directed acyclic graph whose paths correspond to situations referenced from test templates, while ISP RAS's MicroTESK uses MMUSL specifications and graph-based constraint satisfaction (GCSP) to enumerate instruction execution paths and inter-path dependencies.
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Overview
Address translation is a hardware mechanism described in processor architecture specifications alongside interrupt handling and multi-tasking, and is treated as a complex functional unit that must be verified together with the rest of the processor design [1]. Its purpose is to convert addresses produced by software (or by a remote peer) into the addresses actually used by the underlying memory or interconnect hardware. Two principal variants appear in contemporary systems: conventional data address translation used by CPUs, and reverse address translation used by destination nodes that receive remote memory accesses over scale-up fabrics such as NVLink or UALink.
Because the mechanism is exceptionally complex, its verification requires sophisticated test generation tools based on constraint satisfaction [2].
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