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Address Translation

Concept

Address translation is a hardware mechanism that maps addresses between different address spaces. In conventional CPUs it converts data virtual addresses into physical addresses using page tables accelerated by TLBs, and it can also be expressed as PC-indexed translation that uses a load instruction's PC to obtain a page table entry. In distributed multi-GPU scale-up systems, a destination-side variant called reverse address translation maps Network Physical Addresses (NPAs) to System Physical Addresses (SPAs) using Link MMUs and Link TLBs. The article also covers specification-based test program generation for MMUs (MicroTESK, MMUSL) and IBM's DeepTrans/Genesys-Pro approach, which models address translation as a directed acyclic graph whose paths correspond to translation situations referenced from test templates.

First seen 6/13/2026
Last seen 8/16/2026
Evidence 6 chunks
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Overview

Address translation is a hardware mechanism described in processor architecture specifications alongside interrupt handling and multi-tasking, and is treated as a complex functional unit that must be verified together with the rest of the processor design [1]. Its purpose is to convert addresses produced by software (or by a remote peer) into the addresses actually used by the underlying memory or interconnect hardware. Two principal variants appear in contemporary systems: conventional data address translation used by CPUs, and reverse address translation used by destination nodes that receive remote memory accesses over scale-up fabrics such as NVLink or UALink.

Data Address Translation

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RELATIONSHIPS

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DeepTrans ← implements 90% 1e
DeepTrans uses a specification language to depict address translation as a DAG
memory management unit part of → 95% 1e
Address translation is a key mechanism of the MMU

LINKED ENTITIES

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DeepTrans IMPLEMENTS Extracted graph relationship
memory management unit PART_OF Extracted graph relationship

CITATIONS

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22 citations — click to expand
[1] Address translation is one of the main hardware mechanisms described in a processor's architecture specification, alongside interrupt handling and multi-tasking. Test program generator - International Business Machines Corporation
[2] Modern computer architectures treat address translation as a complex functional unit whose behavior must be verified together with the rest of the processor design. Test program generator - International Business Machines Corporation
[3] In conventional processors, address translation converts a data virtual address into a physical address by looking up a page table entry, accelerated by a DTLB with an STLB on misses. PC-Indexed Data Address Translation
[4] PCAX uses the PC of a load instruction, not the data virtual address, to obtain the PTE for the data accessed by a load instruction, and is intended for a small subset of static loads. PC-Indexed Data Address Translation
[5] With PCAX, the effective DTLB miss rate can be cut by 2–3× in many cases (and more in some cases), STLB misses are reduced, average performance improves by 1.7%, and data address translation energy is reduced by 7% across 84 server traces. PC-Indexed Data Address Translation
[6] In multi-GPU scale-up pods, Remote Direct Memory Access over fabrics such as NVLink and UALink requires destination-side translation from NPAs to SPAs, termed Reverse Address Translation. Analyzing Reverse Address Translation Overheads in Multi-GPU Scale-Up Pods
[7] Reverse Address Translation is performed by Link MMUs equipped with Link TLBs. Analyzing Reverse Address Translation Overheads in Multi-GPU Scale-Up Pods
[8] Cold TLB misses dominate latency for small latency-sensitive collectives (up to 1.4× degradation), while larger collectives benefit from warmed caches and show diminishing returns from oversized TLBs. Analyzing Reverse Address Translation Overheads in Multi-GPU Scale-Up Pods
[9] Proposed optimizations for reverse address translation include fused pre-translation kernels overlapping translation with computation, and software-guided TLB prefetching. Analyzing Reverse Address Translation Overheads in Multi-GPU Scale-Up Pods
[10] State-of-the-art MMUs are extremely complex devices comprising multi-level address translation and caching, making specification-based TPG one of the most promising directions in microprocessor verification. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[11] IBM's DeepTrans depicts address translation as a DAG whose vertices correspond to process stages and edges to transitions; a path from source to sink defines a translation situation referenced from test templates processed by Genesys-Pro. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[12] MicroTESK is an open-source TPG framework combining an architecture-independent test generation core with an architecture specification/model, and has been applied to several industrial microprocessors where it revealed many critical bugs not detected by random test programs. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[13] MicroTESK uses a dialect of nML for ISA specifications and the dedicated MMUSL language for specifying MMU mechanisms such as TLBs, page tables, table lookup units, and caches. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[14] In MMUSL, address translation can be expressed as a flat segment that performs a direct range-to-physical-address mapping without using TLBs and tables (e.g., the XKPHYS MIPS64 segment). Specification-Based Test Program Generation for MIPS64 Memory Management Units
[15] MMUSL specifies buffers (TLBs, caches, page tables) using parameters including associativity (ways), number of sets (sets), entry format, index function, tag function, and eviction policy. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[16] MMUSL uses constructs such as B(A).hit, E=B(A), and B(A)=E to request segments and buffers when specifying memory access instruction processing. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[17] A MIPS64 MMU specification in MMUSL defines read logic that calls TranslateAddress(va) for address translation and then performs L1 cache hit/miss handling. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[18] MicroTESK analyzes MMUSL specifications to extract all possible instruction execution paths and inter-path dependencies, then uses Ruby-written test templates, symbolic execution, and constraint solving to instantiate test programs. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[19] Domain-specific languages ease extraction of testing knowledge and learning of TPG tools; dynamic languages such as Ruby and Python suit well for describing test templates; constraint-solving performance is a remaining bottleneck. Specification-Based Test Program Generation for MIPS64 Memory Management Units
[20] Verification tasks are described using terms from two domains: the operation domain (operands, instructions, instruction sequences) and the hardware domain (resources and functional units such as registers, memory, address translation, cache, pipeline). Test program generator - International Business Machines Corporation
[21] Operand-level verification tasks related to address translation include accessing an operand address aligned to or crossing a page boundary, causing a page fault, causing a cache hit, and causing a cache miss at a cache line boundary. Test program generator - International Business Machines Corporation
[22] Architecture Verification Programs (AVP) and Implementation Verification Programs (IVP) are generated to exercise both the architectural definition and the implementation of address-translation functional units. Test program generator - International Business Machines Corporation