2026-08-15
1 items 51 entities 64 connections
Processed 51 entities and 64 relations.
Constrained Random Verification Cross-Level Verification Mutation Testing Mutation Coverage Functional Coverage RTL Code Coverage Instruction Sequence Length Mutation Location Mutation Count Virtual Prototype Register-Transfer Level RISC-V Instruction Set Architecture Fuzzing Symbolic Execution Formal Verification Input Stimuli Generation Coverage-Guided Feedback SMT Solver Transaction Level Modeling Device Under Verification CRV Strategy Execution Trace Comparison Value Coverage Immediate Value Coverage Register File Access Coverage Saturation Feedback-Based Verification riscv-dv MicroRV32 Yosys RISC-V VP FORCE-RISCV RISC-V Torture Test RTL Mutation Engine Commercial RTL Simulator Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs Sallar Ahmadi-Pour Luca Müller Rolf Drechsler University of Bremen DFKI GmbH CHIPS Alliance ALU Control Unit Fetch Unit Instruction Decoder Multiply-Divide Unit System-on-Chip Binary-Compatible Executable Mutation Generation Scripts RTL Mutation Engine