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DFKI GmbH

Organization

DFKI GmbH is represented in the supplied evidence through the affiliation “Cyber-Physical Systems, DFKI GmbH” in RISC-V, Instruction Set Simulator, and RTL processor-verification papers. The evidence connects DFKI GmbH to Daniel Große and Rolf Drechsler in the 2019 ISS fuzzing paper, and to Vladimir Herdt and Rolf Drechsler in a 2022 cross-level processor-verification paper.

First seen 5/25/2026
Last seen 6/9/2026
Evidence 7 chunks
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WIKI

DFKI GmbH

Evidence profile

Within the supplied evidence, DFKI GmbH appears through the affiliation “Cyber-Physical Systems, DFKI GmbH, 28359 Bremen, Germany” in technical papers on Instruction Set Simulator and processor verification.[C1][C3]

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NEIGHBORHOOD

4 nodes · 5 edges
graph · DFKI GmbH · depth=1

RELATIONSHIPS

9 connections
Vladimir Herdt ← part of 100% 5e
Vladimir Herdt is also affiliated with DFKI GmbH.
Rolf Drechsler ← part of 100% 5e
Rolf Drechsler is affiliated with DFKI GmbH
Daniel Große ← part of 100% 2e
Daniel Große is also affiliated with DFKI GmbH.
The paper is affiliated with DFKI GmbH.
Christoph Lüth ← part of 100% 1e
Christoph Lüth is affiliated with DFKI GmbH
The paper is affiliated with DFKI GmbH.
The paper is affiliated with DFKI GmbH
The paper is affiliated with DFKI GmbH.

CITATIONS

4 sources
4 citations — click to collapse
[1] The 2019 ISS fuzzing paper lists Cyber-Physical Systems, DFKI GmbH as an affiliation for Daniel Große and Rolf Drechsler, while Vladimir Herdt and Hoang M. Le are listed with University of Bremen only. Verifying Instruction Set Simulators using Coverage-guided Fuzzing
[2] The 2019 paper proposes coverage-guided fuzzing for ISS verification, combining code coverage, functional coverage, and a custom mutation procedure, and reports finding errors in three public RISC-V ISSs including Spike. Verifying Instruction Set Simulators using Coverage-guided Fuzzing
[3] The 2022 cross-level processor-verification paper lists Cyber-Physical Systems, DFKI GmbH as an affiliation for Vladimir Herdt and Rolf Drechsler. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging
[4] The 2022 paper proposes RTL cross-level processor verification using an endless randomized coverage-guided instruction stream, ISS-based tight co-simulation, and Coverage-guided Aging, with a case study on an industrial pipelined 32-bit RISC-V processor. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging