2026-08-18
3 items 84 entities 102 connections
Generating concurrent test-programs with collisions for multi-processor verification for HLDVT 2002 - IBM Research
source →Processed 8 entities and 9 relations.
Processed 36 entities and 40 relations.
Synergistic Processing Unit (SPU) Cell Processor Instruction Set Architecture (ISA) SPU Reference Model Random Test Case Generation Genesys Pro (GPro) Instruction Simulator Pipeline Simulator Verification Environment RTL Simulation Floating-Point Model IEEE 754 Floating-Point Standard Function Coverage DMA Transaction Self-Modifying Code ECC Error Handling Check-pointing Streaming I/O APUOP Common Definition File Mambo Full System Simulator COFF Format Assembler In-Order Processor Yukio Watanabe Balazs Sallay Brad Michael Daniel Brokenshire Hazim Shafi Daisuke Hiraoka Toshiba Corporation IBM Sony Computer Entertainment Inc. An SPU Reference Model for Simulation, Random Test Generation and Verification INTERPRETER_exec() APU_t struct Channel Access Transaction
Processed 40 entities and 53 relations.
ISA-Formal ARM Limited Bounded Model Checking Formal Verification Simulation-Based Verification Instruction Set Architecture (ISA) Pipeline Forwarding Out-of-Order Execution Register Renaming Reorder Buffer Instruction Fusion Dual Issue Pipeline Abstraction Function Pipeline Follower End-to-End Verification Burch-Dill Flushing Refinement Completion Refinement Architecture Explorer Architecture Specification Language (ASL) ARM Architecture Reference Manual RTL (Register Transfer Level) SystemVerilog Subset Behaviour Checking Abstract Functions (Oracle-based Verification) Interface Properties Hand-Written Properties Instruction Sequence (Stimulus) Superscalar Processor Microcontroller (3-stage pipeline) Floating Point Unit (FPU) Monomorphization (Compiler Technique) Constant Propagation Alastair Reid End-to-End Verification of ARM Processors with ISA-Formal ARMv8-A Architecture ARMv8-M Architecture Unconstrained Opcode (Free Stimulus) Assumption-Based Bug Workaround Instruction Class Enumeration Micro-op (micro-operation)