2026-08-19
2 items 98 entities 129 connections
HiFuzz: Hierarchical Reinforcement Learning for Semantic-Aware and Adaptive CPU Fuzzing | alphaXiv
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HiFuzz DifuzzRTL Cascade Hardware Fuzzing Constrained-Random Verification Mutation-Based Fuzzing Constructive Fuzzing Hierarchical Reinforcement Learning Reinforcement Learning Proximal Policy Optimization Semantic-Aware Basic Block Encoding Adaptive Coverage Reward Mechanism Upper Confidence Bound Multi-Armed Bandit Bidirectional LSTM Sparse Reward Problem Intrinsic Reward Coverage Masking Effect Design Under Test Golden Reference Model Program Agent Basic Block Agent Test Program Generation Instruction Set Architecture RISC-V Structured Tokenizer Dependency Chain Instruction Prevalence Hardware Coverage Formal Verification Out-of-Order Execution Rocket Core BOOM Core CVA6 Cascade: CPU Fuzzing via Intricate Program Generation DifuzzRTL: Differential Fuzz Testing to Find CPU Bugs Proximal Policy Optimization Algorithms Between MDPs and Semi-MDPs: A Framework for Temporal Abstraction in Reinforcement Learning Finite-Time Analysis of the Multiarmed Bandit Problem F. Solt K. Ceesay-Seitz K. Razavi J. Schulman F. Wolski P. Dhariwal A. Radford O. Klimov R. S. Sutton D. Precup S. Singh P. Auer N. Cesa-Bianchi P. Fischer USENIX Security Symposium
Processed 44 entities and 78 relations.
RISC Whisk Nandita Singh Matthew Hicks Angelos Stavrou Wenjie Xiong hardware fuzzing software fuzzing sparse memory matrix custom mutator input seed random instruction generator constraint block direct programming interface executable binary line coverage coverage-based verification functional verification formal verification emulation-based verification assertion-based verification FPGA-based verification RTL mutation tree instruction set architecture memory modeling wishbone interface black-box fuzzing white-box fuzzing feedback-based fuzzing Program Under Test AFL++ Verilator Picorv Sodor1 Sodor3 Sodor5 Mor1kx RISC-V OpenRISC 1000 architecture hardware-to-software translation Virginia Polytechnic Institute and State University RISC-V Foundation testbench design verification