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MORAL testbench

Tool

A verification component used within the MORAL rad-hard microcontroller project. According to the project presentation, verification was carried out at every step of the design (from RTL simulations to post-synthesis and in FPGA), and a dedicated 'Moral testbench' is shown in the design diagram alongside the RAM, ROM, Clock, Reset, and MIL-1553 / CAN peripherals.

First seen 9/22/2026
Last seen 9/22/2026
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MORAL testbench

Overview

The Moral testbench is the verification testbench component associated with the MORAL rad-hard microcontroller developed for space applications. It supports verification activities spanning the full design flow.

Role in the MORAL project

Within the MORAL microcontroller design flow, the testbench is used to verify the processor core, the FPU, the redesigned MPU, and the integrated peripherals (including the MIL-STD-1553C peripheral designed at IHP). The presentation explicitly states that verification was "carried every step of the design, from RTL simulations to post-synthesis, and in FPGA" (chunk 981823b1-c36d-498f-8e71-8272724e715d).

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CITATIONS

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3 citations — click to collapse
[1] The Moral testbench is the verification environment used for the MORAL rad-hard microcontroller and exercises RAM, ROM, Clock, Reset, MIL-1553, and CAN components. Rad-hard Microcontroller with Open Access ISA for Space Applications
[2] Verification was carried out at every step of the design, from RTL simulations to post-synthesis, and in FPGA. Rad-hard Microcontroller with Open Access ISA for Space Applications
[3] The MORAL project targets IHP 130 nm dual-gate CMOS technology and uses the SG13S/RH PDK for space applications. Rad-hard Microcontroller with Open Access ISA for Space Applications