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MORAL testbench

Tool WIKI v1 · 9/22/2026

A verification component used within the MORAL rad-hard microcontroller project. According to the project presentation, verification was carried out at every step of the design (from RTL simulations to post-synthesis and in FPGA), and a dedicated 'Moral testbench' is shown in the design diagram alongside the RAM, ROM, Clock, Reset, and MIL-1553 / CAN peripherals.

MORAL testbench

Overview

The Moral testbench is the verification testbench component associated with the MORAL rad-hard microcontroller developed for space applications. It supports verification activities spanning the full design flow.

Role in the MORAL project

Within the MORAL microcontroller design flow, the testbench is used to verify the processor core, the FPU, the redesigned MPU, and the integrated peripherals (including the MIL-STD-1553C peripheral designed at IHP). The presentation explicitly states that verification was "carried every step of the design, from RTL simulations to post-synthesis, and in FPGA" (chunk 981823b1-c36d-498f-8e71-8272724e715d).

Components exercised by the testbench

A block diagram of the MORAL verification environment lists the following elements connected to the Moral testbench:

  • RAM
  • ROM
  • Clock
  • Reset
  • MIL-1553 peripheral
  • CAN peripheral

A label on the diagram also indicates "Control valid (SUM Copy)", suggesting the testbench provides stimulus and checks sums/copies against expected values.

Target technology context

The MORAL microcontroller — and therefore its testbench — targets IHP's 130 nm dual-gate CMOS process (chunk 981823b1-c36d-498f-8e71-8272724e715d). The project leverages the IHP SG13S/RH PDK for space applications, which provides:

  • SiGe HBTs with npn peak fT/fMAX of 220/340 GHz
  • 130 nm dual-gate-oxide CMOS (VDD = +1.2 V, +3.3 V; TOX = 2 nm / 7 nm)
  • The IHP IXC013RH standard-cell core and IO library (~90 cells)
  • Radiation-hardened-by-design (RHBD) IHP cells with SEL threshold > 65 MeV·cm²/mg and TID tolerance of 100 krad(Si) – 300 krad(Si)

Verification scope

The presentation enumerates verification coverage across:

  1. RTL simulations
  2. Post-synthesis simulations
  3. FPGA-based prototyping

See also

References

  • ESA AMICSA 2022 presentation: "Rad-hard Microcontroller with Open Access ISA for Space Applications"

CITATIONS

3 sources
3 citations
[1] The Moral testbench is the verification environment used for the MORAL rad-hard microcontroller and exercises RAM, ROM, Clock, Reset, MIL-1553, and CAN components. Rad-hard Microcontroller with Open Access ISA for Space Applications
[2] Verification was carried out at every step of the design, from RTL simulations to post-synthesis, and in FPGA. Rad-hard Microcontroller with Open Access ISA for Space Applications
[3] The MORAL project targets IHP 130 nm dual-gate CMOS technology and uses the SG13S/RH PDK for space applications. Rad-hard Microcontroller with Open Access ISA for Space Applications