Interleaved Warp Generation

Technique

Interleaved Warp Generation is a SIMT program synthesis technique used by FuzzGPU to construct valid GPU test programs in which multiple warps share a single instruction stream while respecting the GPU execution model. It pairs an intra-warp linearization based on a generation stack with an inter-warp loop that switches between warps at memory instructions, exposing cross-thread memory conflicts and microarchitectural non-determinism for differential testing against an instruction-set simulator.

First seen 9/29/2026

Last seen 9/29/2026

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Interleaved Warp Generation

Overview

Interleaved Warp Generation is a technique for synthesizing valid SIMT (Single Instruction, Multiple Thread) programs in which the instruction streams of multiple warps are interleaved into a coherent shared program. It is introduced and employed by FuzzGPU, an open-source GPU hardware fuzzer that performs differential testing between a design-under-test (DUT) and an instruction-set-simulator-based golden reference model (GRM) ^[1].

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NEIGHBORHOOD

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graph · Interleaved Warp Generation · depth=1

RELATIONSHIPS

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FuzzGPU ← implements 90% 2e

FuzzGPU interleaves per-warp generation and pauses at memory ops to reason about conflicts.

Load-Store Replay Mechanism ← part of 90% 1e

Interleaved warp generation incorporates a load-store replay mechanism to induce address collisions.

LINKED ENTITIES

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FuzzGPU IMPLEMENTS Extracted graph relationship

Load-Store Replay Mechanism PART_OF Extracted graph relationship

CITATIONS

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7 citations — click to expand

[1] FuzzGPU decomposes SIMT program generation into a novel top-down process with a top-level loop planning overall program structure and a bottom-level loop generating each warp's instruction stream. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX

[2] Each warp's instruction stream is linearized using a generation stack tracking TMASK, NT, and R, yielding a valid thread interleaving under a shared GPC. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX

[3] FuzzGPU implements an interleaved warp generation loop in which warps emit instructions in intra-warp linear order, pause at memory instructions, and switch to another warp. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX

[4] A load is classified as conflicting if it reads an address that another thread has written or will write, and conflicting loads are tainted as a source of non-determinism. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX

[5] A load-store replay mechanism keeps a history of effective addresses from the last k memory instructions and induces an address collision by sampling a previously observed address A and choosing imm = A - V. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX

[6] A barrier planner pre-constructs a global barrier program order by sampling a globally unique sequence of (id, scope) records and enforcing a consistent barrier-ID sequence across warps to avoid interleaving-induced deadlock cycles. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX

[7] Registers and memory addresses are tainted when their hardware value may legally differ from the ISS due to unmodeled microarchitectural timing and cross-thread memory conflicts, allowing lawful DUT/GRM divergence during differential testing. [PDF] Fuzzing Open-Source GPU Hardware with SIMT Program ... - USENIX