Randomized test strategy

Technique

A static test-generation approach in which tests or instruction streams are produced by drawing inputs at random from a distribution that does not change over time. It is widely used in hardware and processor verification (e.g., RISC-V DV, riscv-torture) because of its simplicity and bug-hunting capability, but its static nature tends to over-favor some test state spaces while leaving others nearly uncovered, motivating coverage-guided enhancements such as Coverage-guided Aging.

First seen 6/2/2026

Last seen 9/22/2026

Evidence 4 chunks

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WIKI

Randomized Test Strategy

Definition

A randomized test strategy is a test-generation technique in which the next test input (or next instruction in an instruction stream) is drawn from a fixed probability distribution that does not adapt over time. Because the distribution is static, the strategy itself does not change as testing progresses.

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RELATIONSHIPS

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Cross-level processor verification via endless randomized instruction stream generation with coverage-guided aging ← compares with 95% 2e

The paper compares its coverage-guided approach against a simple randomized test strategy.

InstrGen ← implements 100% 2e

InstrGen is based on a randomized test strategy for instruction generation.

riscv-torture ← uses 55% 2e

Existing instruction stream generators like riscv-torture rely on simple randomized strategies without runtime coverage feedback.

riscv-dv ← uses 60% 1e

The instruction stream generators in the discussed setup rely on a simple randomized test strategy, limiting guided coverage.

LINKED ENTITIES

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riscv-dv USES Extracted graph relationship

riscv-torture USES Extracted graph relationship

CITATIONS

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7 citations — click to expand

[1] RISC-V DV's instruction stream generators are based on a simple randomized test strategy and do not collect/employ runtime coverage information. RISC-V Processor Verification with Coverage-guided Aging

[2] The random test generator used in cross-level processor verification is a re-implementation of riscv-torture's generator and is based on a static randomized test strategy that does not change over time. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[3] The random test generator tends to favor specific test state spaces, producing substantial peaks in some instruction-group combinations and leaving others nearly uncovered. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[4] The random (static randomized test strategy) generator has demonstrated excellent bug-hunting capabilities. Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging

[5] riscv-torture is the UCB-BAR RISC-V torture test generator referenced in the cross-level verification work. RISC-V Processor Verification with Coverage-guided Aging

[6] Randomized testing strategies are used in the formal 'Complexity of Coverage' study specifically because deterministic maximal-coverage strategies for reset games require exponentially large memory. The Complexity of Coverage

[7] Adaptive random testing combined with dynamic domain partitioning reduces invalid-input generation in path-coverage test data generation. Enhancing Path-Oriented Test Data Generation Using Adaptive Random Testing Techniques