SystemC TLM
ConceptSystemC TLM is evidenced here as the implementation basis for the RISC-V VP virtual prototype, which is used as a reference instruction set simulator in a processor-verification co-simulation workflow.
First seen 5/26/2026
Last seen 5/29/2026
Evidence 1 chunks
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Overview
In the provided evidence, SystemC TLM is specifically identified as the technology in which RISC-V VP is written. RISC-V VP is described as a virtual prototype that supports many RISC-V instruction sets and was used as the reference ISS in a co-simulation-based processor verification case study. [C1]
Role in co-simulation
NEIGHBORHOOD
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1 connectionsSystemC TLM is the modeling framework used for the RISC-V VP reference model.
CITATIONS
3 sources3 citations — click to collapse
[1] RISC-V VP is a virtual prototype written in SystemC TLM and supports many RISC-V instruction sets. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[2] The verification setup translated an RTL core to C++ using Verilator and embedded it with the ISS into a common SystemC testbench to enable co-simulation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing
[3] SystemC is reported as lacking functionality to reset the whole simulation including the scheduler, which motivated the use of AFL 2.56b as an out-of-process fuzzer baseline. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing