Overview

In the provided evidence, SystemC TLM is specifically identified as the technology in which RISC-V VP is written. RISC-V VP is described as a virtual prototype that supports many RISC-V instruction sets and was used as the reference ISS in a co-simulation-based processor verification case study. [C1]

Role in co-simulation

The cited verification setup used a RISC-V RTL processor core as the device under test and an ISS extracted from RISC-V VP as the reference model. To enable co-simulation, the RTL core was translated to C++ with Verilator and embedded together with the ISS into a common SystemC testbench. [C2]

Practical limitation noted in the evidence

The evidence notes a SystemC-specific limitation: SystemC has no functionality to reset the whole simulation including the scheduler. In the reported evaluation, this influenced the fuzzing setup, leading the authors to use the out-of-process fuzzer AFL 2.56b as a baseline. [C3]

Evidence-bounded characterization

Within the supplied material, SystemC TLM is therefore best characterized as a modeling and simulation technology used by RISC-V VP in a cross-level processor verification workflow involving RTL-to-C++ translation, ISS-based reference execution, and a shared SystemC testbench. [C1][C2]