2026-09-05
2 items 93 entities 123 connections
From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
source →Processed 42 entities and 51 relations.
RVVTS Automated Failure Categorization RISC-V Vector Extension Ara vector processor coverage-guided test generation single-instruction isolation positive testing negative testing RISC-V Vector Tests Generator RISCV-DV FORCE-RISCV Spike Verilator RTL verification functional coverage grammar-based test generation code minimization Machine State AraRunner Ara test harness CVA6 ELF binary SIMD constraint solving Universal Verification Methodology co-simulation riscvOVPsim Sail-RISC-V CHIPS Alliance Johannes Kepler University Linz DFKI Bremen Manfred Schlägl Jonas Reichhardt Daniel Grosse Valid Sequences test set Invalid+Valid Sequences test set failure mode category symbolic execution RISC-V Torture Test Generator RISC-V VP++ QEMU From Generation to Failure Categorization: An Open-Source automated RTL Verification Framework for RVV
Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking
source →Processed 51 entities and 72 relations.
Registered Report: Generating Test Suites for GPU Instruction Sets through Mutation and Equivalence Checking Shoham Shitrit Sreepathi Pai University of Rochester GPU instruction set formal semantics mutation testing equivalence checking test suite generation model-based test generation bounded model checking stratified random sampling executable semantics PTX instruction set NVIDIA CBMC MUSIC SAIL K framework libFuzzer KLEE SeaHorn LLBMC MiniSAT CVC4 CVC3 mutation score counterexample generation floating-point arithmetic IEEE floating point semantics undefined behaviour non-determinism differential testing coverage-guided fuzzing dynamic symbolic execution litmus tests instruction set simulator SMT-LIB SAT/SMT solvers add.rm.ftz.sat.f32 C semantics test suite generation pipeline path coverage ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS A Complete Formal Semantics of x86-64 User-level Instruction Set Architecture ISA formal semantics x86 instruction set RISC-V ARMv8 instruction set subnormal floating point numbers differential symbolic execution LLVM