2026-09-01
2 items 110 entities 139 connections
Processed 51 entities and 68 relations.
GenHuzz Hardware-Guided Reinforcement Learning hardware fuzzing whitebox fuzzing differential testing Proximal Policy Optimization reinforcement learning coverage-based fuzzing RISC-V assembly instruction generation RISC-V ISA test case generation hardware coverage feedback intra-instruction semantics inter-instruction semantics reward function fuzzing policy mutation-based instruction generation Golden Reference Model RTL simulation Device Under Test word-level tokenization reset module for exploration-exploitation balance Physical Memory Protection Load-Reserved/Store-Conditional instructions cross-entropy loss minimization mismatch detection DifuzzRTL TheHuzz ChatFuzz Cascade Spike RISC-V ISA simulator RocketChip Boom CVA6 GPT-2 GPT-based language model fuzzer transformer architecture FSM coverage condition coverage line coverage Lichao Wu Mohamadreza Rostami Huimin Li Jeyavijayan Rajendran Ahmad-Reza Sadeghi Technical University of Darmstadt Texas A&M University RISC-V 32/64-bit ISA training dataset instruction tokenization and encoding execution trace comparison coverage-based fuzzing
Processed 59 entities and 71 relations.
RISCVuzz Differential CPU Fuzzing Instruction Sequence Generation Bottom-Up Instruction Space Exploration Encoding-Based Instruction Filtering Majority Vote Differential Analysis Static Binary Compilation for Noise Removal Sandbox State Protection Lazy Page Mapping Alarm-Based Infinite Loop Prevention Post-Silicon Fuzzing RTL Fuzzing RISC-V ISA Architectural CPU Vulnerability Halt-and-Catch-Fire CPU Vulnerability GhostWrite RISC-V Vector Extension XTheadMemIdx Extension Instruction Space Coverage Non-Determinism in Instruction Effects Differential Fuzzing Physical Memory Write Primitive Virtual Memory Bypass Transient-Execution Attack MMIO Privilege Levels in RISC-V Paging and Virtual Memory Reproducer File Instruction Encoding Space CSR Instructions QEMU Cascade DifuzzRTL RISC-V Opcodes Repository Nix Build System rvv-bench RISCVuzz Client (C and RISC-V Assembly) RISCVuzz Server Runner Sandbox RISCVuzz: Discovering Architectural CPU Vulnerabilities via Differential Hardware Fuzzing Fabian Thomas Lorenz Hetterich Ruiyi Zhang Daniel Weber Lukas Gerlach Michael Schwarz CISPA Helmholtz Center for Information Security T-Head SiFive Scaleway T-Head XuanTie C906 CPU T-Head XuanTie C908 CPU T-Head XuanTie C910 CPU SiFive U54 CPU SiFive U74 CPU vse128.v Instruction Fuzzing Throughput Optimization Multi-Core Fuzzing Parallelization Sequence Length Scaling