RISC-V Compliance Suite

Tool

The RISC-V Compliance Suite is a collection of compliance tests produced under the auspices of the RISC-V International Association. It serves as one class of stimulus input in RISC-V processor hardware design verification (DV) flows, where an RTL implementation is compared against a golden reference model such as the Imperas riscvOVPsim. The suite is typically combined with directed tests and constrained-random Instruction Stream Generator (ISG) tests (e.g., the Google open-source RISC-V DV-ISG) to provide comprehensive verification coverage of the open RISC-V ISA. It is hosted in a public Git repository (e.g., the riscv-compliance / riscv-compliances repository) and is cloned as one of the first steps of a combined verification flow, with the RV32I compliance test suite being a common baseline configuration.

First seen 9/24/2026

Last seen 9/27/2026

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WIKI

RISC-V Compliance Suite

The RISC-V Compliance Suite is a collection of compliance tests produced under the auspices of the RISC-V International Association. It is intended to address a specific challenge that arises from the openness of the RISC-V ISA: because RISC-V permits many configuration options and custom extensions, there is no single ISA owner with a unilateral interest in ensuring cross-implementation compatibility. Open ISAs such as RISC-V must therefore pioneer compliance collectively, in contrast to established ISAs that are controlled by single companies.

Role in Processor Design Verification

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RV32I compliance test suite ← part of 72% 2e

The RV32I compliance test suite is a component within the broader RISC-V Compliance Suite.

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RV32I compliance test suite PART_OF Extracted graph relationship

CITATIONS

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[1] The RISC-V Compliance Suite is a collection of compliance tests produced under the auspices of the RISC-V International Association, used in processor verification flows to compare RTL against golden reference models. Previous wiki article (v1) source

[2] In a combined verification flow, the compliance suite is cloned from a public Git repository (e.g., riscv-compliances) and the RV32I compliance test suite is run as the first stimulus class, followed by ISG-generated tests, ELFs compiled for both RTL and reference model (riscvOVPsim), and log comparison reporting pass/fail and mismatching instructions. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification

[3] The RV32I compliance test suite consists of 55 per-instruction and per-architectural checks (e.g., I-LW-01, I-SW-01, I-ADD-01, I-SUB-01, I-MISALIGN_JMP-01, I-RF_size-01, I-RF_x0-01) and a passing run reports OK: 55/55. Rolling the Dice with Random Instructions is the Safe Bet on RISC-V Verification

[4] Typical RISC-V processor verification plans combine the RISC-V International Association Compliance suite, directed tests, and constrained-random ISG tests such as the Google open-source RISC-V DV-ISG. Previous wiki article (v1) source

[5] Mellanox Technologies publicly disclosed using Imperas RISC-V verification tools and reference models in its design verification flow, with the RISC-V Compliance Suite cited as one of the stimulus inputs used in step-and-compare verification. Previous wiki article (v1) source