ARM

Concept

ARM is a widely deployed processor architecture that appears across the provided evidence in several distinct roles: as a comparator microarchitecture in discussions of RISC-V verification maturity, as a target ISA (ARM-v6m) supported by the ExactStep instruction-set simulator, as both host and guest in ARM-on-ARM hardware-assisted virtualization using Linux KVM within SystemC-TLM virtual platforms, and as the foundation for the ARM Compute Library (ARM-CL) used to accelerate transformer and CNN inference on ARM-based heterogeneous multi-processor system-on-chips (HMPSoCs) at the edge.

First seen 5/27/2026

Last seen 7/10/2026

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ARM

ARM is a processor architecture referenced in the provided evidence across simulation, virtualization, edge inference, and verification-comparison contexts. The evidence does not characterize ARM's internal microarchitecture directly; instead, it situates ARM within specific tools, platforms, and comparison points.

ARM as a comparator microarchitecture

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RELATIONSHIPS

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RISC-V compares with → 88% 1e

RISC-V is presented as a reliable and secure alternative to ARM microarchitectures.

LINKED ENTITIES

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RISC-V comparator_microarchitecture The RISC-V verification source explicitly names ARM alongside x86 as the microarchitectures to which RISC-V is compared as an alternative.

x86 co_comparator_microarchitecture x86 is listed alongside ARM as one of the established microarchitectures against which RISC-V is positioned in the verification-maturity discussion.

ExactStep supported_target_ISA ExactStep's README explicitly lists ARM-v6m as a supported architecture, alongside RISC-V and MIPS, with usage flags for `--march armv6`.

SystemC TLM virtual_platform_framework The multicore CPU model that replaces the ISS is implemented as a SystemC-TLM-based model used as a drop-in replacement in virtual platforms.

CITATIONS

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5 citations — click to expand

[1] ARM is referenced as one of the microarchitectures (alongside x86) against which RISC-V is positioned as a reliable and secure alternative, and whose verification-maturity challenges (speculative execution, out-of-order execution, pipeline complexity, Spectre/Meltdown-class vulnerabilities) motivate hybrid simulation-plus-formal verification strategies. RISC-V Microarchitecture Verification Approaches

[2] ARM-v6m is one of the ISAs supported by ExactStep, listed alongside RISC-V (RV32IMAC, RV64IMAC) and MIPS (mips-i), with `--march armv6` accepted as a machine variant; the simulator executes one instruction per `cpu::step()` call and is intended for cosimulation and System-C bus interfacing rather than raw execution performance. ultraembedded/exactstep - Instruction Accurate Instruction Set Simulator

[3] ARM-on-ARM virtualization in SystemC-TLM virtual platforms runs target software natively on ARM-based hosts using Linux KVM and ARM hardware virtualization extensions, eliminating the ISS on the host and yielding up to 10x speedup over ISS-based virtual platforms on compute-intensive workloads (and >100x depending on benchmark) via a multicore SystemC-TLM CPU model. High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms

[4] The ARM Compute Library (ARM-CL) provides low-latency CNN inference on ARM-based edge devices; new transformer kernels added to ARM-CL achieve up to 3x faster transformer inference versus state-of-the-art CPU/GPU implementations on an ARM-based embedded board. Fast Transformer Inference on ARM-Based HMPSoCs

[5] On ARM-based HMPSoCs combining an embedded ARM CPU with an on-chip GPU, cooperative CPU-GPU transformer inference (memory-intensive ops on ARM CPU, compute-intensive ops on GPU) further reduces transformer inference latency by up to 15.72% versus the best single-processor ARM-CL inference path. Fast Transformer Inference on ARM-Based HMPSoCs