ARM

ARM is a processor architecture referenced in the provided evidence across simulation, virtualization, edge inference, and verification-comparison contexts. The evidence does not characterize ARM's internal microarchitecture directly; instead, it situates ARM within specific tools, platforms, and comparison points.

ARM as a comparator microarchitecture

In the RISC-V microarchitecture-verification literature provided, ARM functions primarily as an established commercial microarchitecture against which the maturity of RISC-V verification is measured. The source argues that addressing RISC-V verification challenges is important for establishing RISC-V as a reliable and secure alternative to other microarchitectures, including ARM and x86. [ARM-as-comparator]

The same source frames RISC-V verification complexity in terms that also apply to ARM-class designs: processor verification should not be reduced to checking whether instructions execute correctly; the microarchitecture and pipeline are the central verification challenges; and higher-performance techniques such as speculative execution and out-of-order execution increase complexity and expose potential security vulnerabilities such as Spectre and Meltdown. The source motivates hybrid verification approaches that combine simulation with formal verification for subunits such as branch predictors, pipeline components, caches, prefetch buffers, ALUs, register models, and load-store units. [Microarchitecture-verification-challenges, Formal-and-hybrid-verification]

ARM in instruction-set simulation

In the ExactStep instruction-set simulator, ARM is one of three supported ISAs alongside RISC-V (RV32IMAC, RV64IMAC) and MIPS (mips-i). The specific ARM variant currently listed as supported is ARM-v6m, with the project noting that "others [are] to come soon." ExactStep is described as an instruction-accurate simulator that executes one instruction per call to cpu::step(), in contrast to dynamic-binary-translation emulators such as QEMU. It is intended for cosimulation, peripheral development, and System-C bus interfacing rather than raw execution performance, and it can be used to run bare-metal executables compiled for the supported ISAs. [ExactStep-ARM-v6m]

ARM-on-ARM hardware-assisted virtualization

The provided arXiv work "High-Performance ARM-on-ARM Virtualization for Multicore SystemC-TLM-Based Virtual Platforms" describes a methodology that targets ARM-based hosts running target software natively using Linux KVM, eliminating the need for an instruction-set simulator on the host side. The paper presents a multicore SystemC-TLM-based CPU model intended as a drop-in replacement for an instruction-set simulator within virtual platforms, with no special requirements on the host system beyond the ARM hardware virtualization extensions. Reported benchmark results indicate up to a 10x speedup over traditional ISS-based virtual platforms on compute-intensive workloads, with speedups exceeding 100x depending on the benchmark. [ARM-on-ARM-virtualization]

In this context ARM appears in three roles simultaneously: as the host ISA that runs the virtual platform, as the guest ISA of the target software, and as the architecture whose hardware virtualization extensions underpin KVM acceleration.

ARM-based heterogeneous edge inference

The provided arXiv work "Fast Transformer Inference on ARM-Based HMPSoCs" positions ARM as the basis for low-latency on-device inference on resource-constrained edge devices. The ARM Compute Library (ARM-CL) framework is described as providing low-latency CNN inference on ARM-based edge devices, and the paper extends ARM-CL with new transformer kernels so that transformer inference can run natively on ARM CPUs. The reported result is up to three times faster transformer inference versus state-of-the-art CPU/GPU implementations on an ARM-based embedded board. [ARM-CL-transformer]

The same paper discusses heterogeneous multi-processor system-on-chips (HMPSoCs) that combine embedded ARM CPUs with on-chip GPUs, and introduces a cooperative CPU-GPU scheduling policy in which memory-intensive transformer operations run on the ARM CPU and highly parallelizable, compute-intensive operations run on the GPU. This cooperative execution is reported to further reduce transformer inference latency by up to 15.72% over the best single-processor ARM-CL inference path. [ARM-HMPSoC-cooperative]

Summary of roles in the evidence

Across the supplied sources, ARM is treated as: (1) a benchmark microarchitecture for evaluating RISC-V verification maturity; (2) a simulator target ISA (ARM-v6m in ExactStep); (3) both host and guest in KVM-accelerated SystemC-TLM virtual platforms; and (4) the CPU ISA underlying the ARM Compute Library and the ARM/GPU HMPSoCs used for on-chip transformer inference.