BlackParrot
ToolFirst seen 6/6/2026
Last seen 7/11/2026
Evidence 20 chunks
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22 connectionsBlackParrot is a RV64GC processor implementing the RISC-V ISA
BlackParrot is designed in SystemVerilog HDL.
Zynq-Parrot enables emulation/prototyping of BlackParrot on FPGA boards
Condominium is used for verification and optimization of BlackParrot
BlackParrot has a Branch History Table and Branch Target Buffer for branch prediction
BlackParrot implements cache coherence through its Memory End
BlackParrot integrates verification methods into its CI routines
BlackParrot performance optimization uses SPEC benchmarks
BlackParrot verification uses Linux boot as a key functional test
ZP Cosim was applied to and evaluated against the BlackParrot processor, discovering 4 bugs
ProcessorFuzz is evaluated using the BlackParrot processor.
BlackParrot uses CoreMark for benchmarking
BlackParrot provides built-in event-driven performance counters
BlackParrot includes an instruction TLB for virtual-to-physical address translation
A bug was found in BlackParrot related to NaN-boxing of floating-point values.
The ProcessorFuzz paper evaluates the tool on the BlackParrot processor.
BlackParrot implements the RISC-V instruction set architecture.
The catch-up ALU is a case study component within BlackParrot studied via Condominium
BlackParrot Memory End implements the Bedrock protocol for cache coherence
BlackParrot Front End includes a PC generation module
BlackParrot Front End contains the instruction cache
BlackParrot is a processor designed at Bespoke Silicon Group