Cache Coherence

Concept

Cache coherence is the mechanism that ensures data consistency across multiple caches in multi-core systems, enabling shared data access and reducing task computation time. It is implemented via coherence protocols (such as the open-source BedRock protocol using MOESIF states), local cache engines (LCEs), programmable cache coherence engines (CCEs), and coherence-aware Network-on-Chip (NoC) routing, and its incorrect enforcement can cause stale data, corruption, or stalls.

First seen 5/25/2026

Last seen 7/11/2026

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Overview

Cache coherence is the property that maintains data consistency across multiple caches in a multi-core system. It enables data sharing among caches and substantially reduces task computation time.^[1] In multi-core cache systems, when multiple accesses target the same cache line, coherence must be enforced correctly to preserve correctness.^[2]

Coherence Protocols

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BlackParrot part of → 95% 2e

BlackParrot implements cache coherence through its Memory End

Multi-Core Validation ← uses 93% 1e

Multi-core validation verifies cache coherence and memory ordering.

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Multi-Core Validation USES Extracted graph relationship

CITATIONS

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[1] Cache coherence is essential for data consistency, enables data sharing among caches, and substantially reduces task computation time. Learning Cache Coherence Traffic for NoC Routing Design

[2] In multi-core cache systems, when multiple accesses target the same cache line, coherence must be enforced correctly to preserve correctness, and failures can cause stale data, data corruption, or stalls. Capability Hardware Enhanced RISC-V Instruction Set Architecture (UCAM-CL-TR-984)

[3] The BedRock protocol uses MOESIF coherence states, eliminates transient coherence states, and has been implemented as fixed-function, microcode-programmable, and hybrid directory engines in the BlackParrot-BedRock (BP-BedRock) system. The Open-Source BlackParrot-BedRock Cache Coherence System

[4] The BedRock coherence system is composed of a coherence network, local cache engines (LCEs) that manage coherence for individual L1 caches, and cache coherence engines (CCEs) that act as programmable microcoded coherence directories for subsets of memory address space. BlackParrot Dissertation (University of Washington)

[5] A BlackParrot CCE contains 8 64-bit general-purpose registers, a miss status handling register, coherence network ports, dedicated coherence directory storage, speculative memory access tracking storage, and pending bit storage, with fetch and execute pipeline stages. BlackParrot Dissertation (University of Washington)

[6] A BlackParrot tile contains a core, a cache coherence engine, and an L2 slice; coherent accelerator tiles, L2 extension tiles, and streaming/I/O tiles all attach to the shared coherence network. BlackParrot Dissertation (University of Washington)

[7] Cache coherence is often overlooked in NoC routing, motivating the Cache Coherence Traffic Analyzer (CCTA) and a coherence-aware routing approach that achieves up to 10.52% lower packet latency, 55.51% faster execution time, and 49.02% total energy savings. Learning Cache Coherence Traffic for NoC Routing Design

[8] OpenXiangShan performs multi-core validation of cache coherence and memory ordering using XSNoCDiffTopConfig and dual-core NEMU, and tracks performance regressions via SPEC CPU 2006 checkpoints and IPC measurement. Difftest and Co-Simulation | OpenXiangShan/XiangShan | DeepWiki