Cache Coherence

Concept

Cache coherence is the mechanism that ensures data consistency across multiple caches in multi-core systems, enabling shared data access and reducing task computation time. It is implemented via coherence protocols (such as the open-source BedRock protocol using MOESIF states), directory engines, and coherence-aware Network-on-Chip (NoC) routing, and its incorrect enforcement can cause stale data, corruption, or stalls.

First seen 5/25/2026

Last seen 6/8/2026

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Overview

Cache coherence is the property that maintains data consistency across multiple caches in a multi-core system. It enables data sharing among caches and substantially reduces task computation time.^[1] In multi-core cache systems, when multiple accesses target the same cache line, coherence must be enforced correctly to preserve correctness.^[2]

Coherence Protocols

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RISC-V deployment_target BP-BedRock targets the BlackParrot 64-bit RISC-V multicore, and coherence is a recognized concern in RISC-V verification.

CITATIONS

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[1] Cache coherence is essential for data consistency and substantially reduces task computation time by enabling data sharing among caches in multi-core systems. Learning Cache Coherence Traffic for NoC Routing Design

[2] Routing in multi-core systems serves two roles — facilitating data sharing (influenced by topology) and managing NoC-level communication — and cache coherence is often overlooked in routing. Learning Cache Coherence Traffic for NoC Routing Design

[3] Two main challenges in cache-coherence-aware NoC design are the lack of specialized tools to assess cache coherence's impact and the neglect of topology selection in routing. Learning Cache Coherence Traffic for NoC Routing Design

[4] A cache coherence-aware routing approach with integrated topology selection guided by the Cache Coherence Traffic Analyzer (CCTA) achieves up to 10.52% lower packet latency, 55.51% faster execution time, and 49.02% total energy savings. Learning Cache Coherence Traffic for NoC Routing Design

[5] BedRock is an open-source cache coherence protocol that employs the canonical MOESIF coherence states and reduces implementation burden by eliminating transient coherence states. The Open-Source BlackParrot-BedRock Cache Coherence System

[6] BedRock's design complexity, concurrency, and verification effort are analyzed and compared to a canonical directory-based invalidate coherence protocol. The Open-Source BlackParrot-BedRock Cache Coherence System

[7] Three cache coherence directories implementing the BedRock protocol within the BlackParrot 64-bit RISC-V multicore processor — collectively called BlackParrot-BedRock (BP-BedRock) — include a fixed-function baseline, a microcode-programmable engine, and a hybrid fixed-function and programmable design. The Open-Source BlackParrot-BedRock Cache Coherence System

[8] Cache coherence conflicts are issues in multi-core caches where multiple accesses to the same line cause stale data, corruption, or stalls if coherence is not enforced correctly. RISC-V Test Generation: Random, Directed & Coverage

[9] Coverage closure is the process of achieving sufficient functional and code coverage to gain confidence that relevant design behaviors — including cache coherence interactions — have been tested during RISC-V verification. RISC-V Test Generation: Random, Directed & Coverage