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STIMSMITH

SystemVerilog UVM test generator

Tool
First seen 9/27/2026
Last seen 9/27/2026
Evidence 1 chunks

NEIGHBORHOOD

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RELATIONSHIPS

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riscv_instr_base_test ← derived from 90% 1e
The assembly test riscv_instr_base_test is produced by the SystemVerilog UVM test generator as part of the flow.