Imperas Instruction Stream Test Generator

Tool

The Imperas Instruction Stream Test Generator is a directed-test generation tool developed by Imperas Software Ltd. as part of its RISC-V Verification IP (VIP) solution. It is used to create architectural validation test suites that verify RISC-V processor designs against the Imperas golden reference model, with open-source suites covering ratified and draft extensions such as RV32/64IMC, RV32F, RV64F, RV64D, RISC-V Vector, Crypto, and Bit Manipulation.

First seen 9/24/2026

Last seen 9/24/2026

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Overview

The Imperas Instruction Stream Test Generator is a tool developed by Imperas Software Ltd. that produces directed-tests used in the architectural validation of RISC-V processor implementations. It forms part of the broader Imperas RISC-V Verification IP (VIP) offering and is used to generate the test suites shipped alongside the Imperas RISC-V golden reference model and the free riscvOVPsimPlus reference simulator.

Role in the Imperas Verification Flow

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CITATIONS

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[1] The Imperas Instruction Stream Test Generator is a directed-test generation tool from Imperas Software Ltd. used in RISC-V Verification IP (VIP) solutions. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[2] The Imperas floating-point architectural validation test suites cover RV32F, RV64F, and RV64D and extend the existing range of tests for ratified and near-ratified RISC-V specifications. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[3] The RISC-V step-and-compare methodology verifies an RTL processor implementation against the Imperas golden reference model within a SystemVerilog UVM environment and covers asynchronous events. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[4] The 1994 Intel Floating Point bug was reported as a $475M pre-tax charge, illustrating the cost impact of late-stage processor bugs. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[5] Open-source test suites generated by the tool total over 3.5 million instructions and cover RV32/64IMC, RV32F, RV64F, RV64D, RISC-V Vector, RV32/64K Crypto 0.8.0 draft, and RV32/64B Bit Manipulation 0.93 draft. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[6] The RISC-V Vector test suite ships with configuration spec:0.8, xlen:32, elen:32, vlen:256, slen:256, FP:IEEE754, and Imperas can provide additional configurations including spec 0.9 and 1.0 draft. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[7] The Imperas test suites are for ISA architectural compliance validation and are not comprehensive hardware design verification suites that prove hardware is bug-free. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[8] The Imperas golden reference model includes built-in monitors that provide instruction and architectural functional coverage metrics without post-simulation processing or log-file analysis. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design

[9] The free riscvOVPsimPlus RISC-V reference model and simulator supports ratified RV32/64 IMAFDC plus near-ratified Vector 'V', Hypervisor 'H', Bit Manipulation 'B', and Crypto (Scalar) extensions. Imperas Leads The RISC-V Processor Verification Ecosystem - Embedded Computing Design