Verification IP
ConceptVerification IP (VIP), in the provided evidence, is discussed in the context of UVM-based subsystem-level testbenches, where multiple UVM agents or VIPs can be mapped across CPU threads in eUVM to exploit multicore parallelism during compute-intensive sequence randomization.
First seen 5/25/2026
Last seen 5/25/2026
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Overview
Verification IP (VIP) is referenced in the provided DVCon evidence as part of UVM-based verification environments: a subsystem-level testbench often contains multiple UVM agents or Verification IPs (VIPs). In the cited eUVM multicore testbench architecture, each VIP/UVM agent may be placed on a separate CPU thread to distribute work across the host processor resources.
Role in multicore UVM testbenches
NEIGHBORHOOD
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1 connectionsVIP level parallelism maps each VIP/uvm agent to a separate CPU thread.
CITATIONS
7 sources7 citations — click to expand
[1] A subsystem-level testbench often has multiple UVM agents or Verification IPs (VIPs). [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[2] In eUVM VIP-level parallelism, each UVM agent can be mapped to a separate CPU thread to distribute sequence randomization. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[3] Sequence randomization is often the most compute-intensive process in a testbench because it involves solving complex constraints. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[4] A parallel simulator uses task executors on separate CPU threads and synchronization barriers to keep task executors synchronized with the scheduler. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[5] The simple multicore testbench architecture applies to testbenches with multiple VIPs and therefore limits parallelism to subsystem-level verification. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[6] Performance gain may be limited when task load is not balanced across executors, including when different types of VIPs are mapped to different executors. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings
[7] eUVM worker threads are free-running asynchronous threads owned by the simulator but decoupled from the scheduler, and data exchange with regular UVM tasks is handled through asynchronous TLM FIFOs. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings