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STIMSMITH
Technique

Technique

902 entities
#
1
Coverage-Guided Fuzzing
60
2
hardware fuzzing
50
3
Symbolic Execution
43
4
differential testing
39
5
Fuzzing
35
6
Formal Verification
34
7
Co-Simulation
27
8
CSR-transition coverage
27
9
constrained random verification
26
10
Mutation-Based Fuzzing
26
11
RTL simulation
21
12
Simulation-Based Verification
20
13
random instruction generation
20
14
Direct Instruction Injection
17
15
Grey-Box Fuzzing
16
16
Coverage-Driven Verification
16
17
Model Checking
16
18
Differential Fuzzing
15
19
Processor Fuzzing
15
20
Constraint Solving
15
21
register coverage
15
22
Model-Based Test Generation
14
23
Coverage-based Greybox Fuzzing
14
24
Constrained-Random Stimulus Generation
13
25
Reinforcement Learning
13
26
Directed Testing
12
27
Constraint Programming
12
28
Runtime Instruction Morphing
12
29
Guided Test Case Generation
12
30
Covariance Matrix Adaptation Evolution Strategy
12
31
ISA simulation
12
32
Asymmetric ISA Pre-Simulation
12
33
Contradiction Analysis
12
34
Bounded Model Checking
12
35
constrained-random test generation
12
36
Object-Oriented Stimulus Generation
11
37
Tandem Simulation
11
38
Synchronizable Co-simulation
11
39
constrained-random instruction generation
11
40
RTL Fuzzing
11
41
Property Checking
11
42
Constraint-Based Randomization
10
43
Constrained-Random Verification (CRV)
10
44
Constrained Random Testing
10
45
Hardware-Guided Reinforcement Learning
10
46
Theorem Proving
9
47
Mutation-Analysis-Guided Fuzzing
9
48
Dynamic Swappable Memory
9
49
Interval Property Checking
9
50
litmus tests
9
51
Contention-guided Hardware Fuzzing
9
52
CPU fuzzing
9
53
Equivalence Checking
9
54
on-the-fly instruction stream generation
9
55
Control Flow Entanglement with Data Flow
9
56
Automatic Property Generation
9
57
Program Reduction
9
58
Batch (tight packing of verification events)
8
59
software fuzzing
8
60
Squash (order-decoupled fusion)
8
61
Differential Information Flow Tracking
8
62
Register-Coverage Guided Fuzzing
8
63
Counterexample Shrinking
8
64
Assertion-Based Verification
8
65
test program generation
8
66
Random Test Program Generation
8
67
Constraint Satisfaction Problem
8
68
constraint-based test generation
8
69
Instruction Scheduling
8
70
Uniform Generation of SAT Witnesses
8
71
Multi-Armed Bandit (MAB)
8
72
Coverage-guided Aging
8
73
Architecture Description
7
74
White-Box Fuzzing
7
75
Ant Colony Optimization
7
76
Top-Down Stimulus Planning
7
77
constraint-based test case generation
7
78
Stimulus Template
7
79
Directed Test Generation
7
80
Mutation Testing
7
81
Bounded Model Checking (BMC)
7
82
Generation-Based Fuzzing
7
83
Replay (lightweight debugging by event retransmission)
7
84
Differential Fuzz Testing
7
85
Selective Symbolic Execution
7
86
transformer language model for instruction sequences
7
87
Error Injection
7
88
stream generation using abstract CSP
7
89
Test Case Generation
7
90
Fault Injection
7
91
Memory Shadowing
7
92
Glitch-aware leakage model
7
93
Multicore Parallelization
7
94
Proximal Policy Optimization
7
95
Model-based Stimuli Generation
7
96
instruction fuzzing
7
97
BDD-based Constraint Solving
7
98
Fuzz Testing
7
99
Test Case Shrinking
7
100
Burch-Dill Correspondence Checking
7
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