Technique
Technique
902 entities#
1 Burch-Dill Correspondence Checking
7 2 Selective Symbolic Execution
7 3 Generic Simulation Method
6 4 Statistical Fault Injection (SFI)
6 5 Hardware-Software Co-Verification
6 6 Pipeline Modeling
6 7 Functional Verification
6 8 Randomized Instruction Generation
6 9 Burch and Dill Pipeline Verification Method
6 10 AI-Assisted Verification
6 11 Dependency Analysis
6 12 Cross-Level Testing
6 13 Multi-target Coverage-based Greybox Fuzzing
6 14 Black-Box Fuzzing
6 15 Object-Oriented Constraint Composition (OOP)
6 16 coverage-directed test generation
6 17 Pseudo-Random Testing
6 18 Reinforcement learning (RL)
6 19 Coverage-Guided Test Generation
6 20 Mux Coverage Instrumentation
6 21 Hierarchical Aggregation and Decoding
6 22 determinism anchors
6 23 SystemVerilog Testbench
6 24 Instruction Morphing
6 25 Mapping Functions
6 26 Coverage-Guided Greybox Fuzzing
6 27 REVERSI
6 28 Register Allocation
6 29 Instruction Stream Generation
6 30 coverage-guided mutation fuzzing
6 31 ISS Code Generation
6 32 Just-in-Time Compiled Simulation
6 33 SAT-based Bounded Model Checking
6 34 Constraint-based Random Simulation
6 35 Directed Test
6 36 UVM
6 37 Template-Based Generation
6 38 decompositional model checking
6 39 Design-for-Test (DfT)
5 40 Variable-Group Indexing
5 41 AI-Driven Test Generation
5 42 CPU-assisted test-case generation
5 43 Randomized Instruction Stream Generation
5 44 Golden Reference Model Comparison
5 45 Intermediate Program Construction
5 46 Constraint Satisfaction Problem Solving
5 47 XOR-based Hash Partitioning
5 48 SMT-based Verification
5 49 Directed-Random Test Generation
5 50 Dynamic Binary Instrumentation
5 51 partial intermediate state verification without re-initialization
5 52 Hardware-based Seed Selection
5 53 satisfiability modulo theories
5 54 Automatic Test Pattern Generation
5 55 Training Derivation Strategy
5 56 Concolic Testing
5 57 Translation Buffer
5 58 reference model comparison
5 59 Large Language Models (LLMs)
5 60 Directed-Random Stimulus
5 61 control-flow anchors
5 62 Automated Design Inspection
5 63 stimulus generation
5 64 Sudoku Constraint Solving
5 65 BDD Weighting Algorithm
5 66 FSM Coverage-Directed Test Generation
5 67 Test Compaction
5 68 SMT-based Constraint Solving
5 69 communicating extended finite state machines
5 70 RISC-V assembly generation
5 71 Maintaining Arc Consistency
5 72 functional coverage measurement
5 73 UVM (Universal Verification Methodology)
5 74 static analysis
5 75 Single Instruction Isolation with Code Minimization
5 76 Deep Q-Network
5 77 coverage-driven generation
5 78 Leakage contracts
5 79 Directed-Random Test Sequence Generation
5 80 Code Generation
5 81 Security-Aware Instruction Stream Post-Processing
5 82 Correspondence Checking
5 83 Pseudo-Random Test Generation
5 84 multiplexer toggle coverage
5 85 Symbolic Ternary Simulation
5 86 single-instruction isolation
5 87 Instruction Scenario Modeling
4 88 Coverage-Driven Instruction Generation
4 89 Consistency Assertions
4 90 Interpretive Simulation
4 91 congestor
4 92 Instruction Distillation
4 93 Pre-silicon fuzzing
4 94 Constraint-based Random Stimuli Generation
4 95 Functional Coverage
4 96 random test-case generation
4 97 Random Test Generation
4 98 Ternary Simulation
4 99 GenerateSolution algorithm
4 100 Control Flow Over-Tainting Mitigation
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