Technique
Technique
365 entities#
1 Consistency Assertions
4 2 Instruction Selection
4 3 Data Assignment
4 4 Modulo Scheduling
4 5 Mux-Coverage Guided Fuzzing
4 6 Cycle-Sensitive Register Coverage
4 7 feedback-based verification methodology
3 8 Mutation-Based Testing
3 9 Completeness Analysis
3 10 Exception Condition Stimulus Planning
3 11 Instruction Scenario Generation
3 12 inversion tactic
3 13 random instruction generation
3 14 Sequence Level Parallelism
3 15 SAT Solving
3 16 Multi-Class Randomization Architecture
3 17 Directed Instruction Stream Generation
3 18 symbolic solver
3 19 Instruction Injection
3 20 Fuzz Testing
3 21 On-the-Fly Instruction Stream Evolution
3 22 RVFI-DII
3 23 Hardware-Based Mutation Strategy
3 24 path enumeration
3 25 RTL Co-simulation
3 26 software fuzzing
3 27 Execution Controller
3 28 Hybrid Verification Methodology
3 29 Parallelized Fork
3 30 Compiled Simulation
3 31 Tandem Execution
3 32 hierarchical constrained-random stimulus generation
3 33 Single-Class Randomization Architecture
3 34 hardware-software parallelism (non-blocking transmission)
3 35 Interrupt Mutation
3 36 Single-Class Randomization
3 37 Random Binary Generation
3 38 Instruction Distillation
3 39 Hierarchical Constrained-Random Test Generation
3 40 SystemVerilog Constrained-Random Testbench
3 41 Variant of Ant Colony Optimization
3 42 Input Instruction Distillation
3 43 Semantic Level Mutation
3 44 Hardware-Based Mutation
3 45 Interruption and Exception Simulation
3 46 Universal Verification Methodology
3 47 VACO
3 48 Field Level Mutation
3 49 Interrupt and Exception Injection
3 50 TIUP
3 51 State Synchronization
3 52 Exception Stimulus Generation
3 53 Maintaining Arc Consistency
3 54 Coverage-Guided Hardware-Software Contract Fuzzing
3 55 UVM-TLM Co-Simulation
3 56 Class-Based Testbench
3 57 Machine Learning for Fuzzing
3 58 Instruction Coverage Analysis (TSVC)
3 59 FPGA-Based Fault Injection
3 60 Polynomial Formal Verification (PFV)
3 61 Dynamic Redundant Load Pruning
3 62 Asynchronous Interrupt Handling
3 63 semantics-aware test case generation
3 64 optimised instruction set tree traversal
3 65 lazy memory synchronisation
3 66 Per-Instruction Mutation
3 67 Deep Reinforcement Learning for Test Generation
3 68 Enhanced Havoc Mutation
3 69 Data Path Modeling
3 70 Multi-Class Randomization
3 71 DPI Interface
3 72 Directed Random Stimuli Generation
2 73 Pseudorandom Generator (PRG) Stimulus Generation
2 74 recurrent neural network-based constraint alteration
2 75 Fast Exploration Mutation
2 76 stimulus generation
2 77 pseudorandom generator (PRG)
2 78 Simulation-based Processor Verification
2 79 Symbolic Execution for Test Generation
2 80 Endless Instruction Stream Generation
2 81 Post-processing Test Vector Clustering
2 82 Constraint-Based Branch Stimulus Generation
2 83 Dynamic Program Analysis
2 84 Object-Oriented Verification
2 85 coverage-directed test generation
2 86 Concolic Testing
2 87 Dedicated DFI Cache
2 88 instruction field mutation
2 89 post-processing trace analysis
2 90 Maintain-Arc-Consistency
2 91 Object-Oriented Constraint Partitioning
2 92 opcode injection
2 93 Register Value Comparison
2 94 user-assisted code generation
2 95 Virtual Coverage
2 96 Model Checking
2 97 Randomized Instruction Stream Generation
2 98 object-oriented constraint-based instruction generation
2 99 Bottom-Up Implementation
2 100 instruction sequence generation
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