Leakage Contracts

Technique

Leakage contracts are an ISA-level abstraction that formally specifies the side-channel leakage behavior of a processor's microarchitecture, enabling modular verification of software security against hardware side channels.

First seen 6/26/2026

Last seen 6/26/2026

Evidence 5 chunks

Wiki v1

WIKI

Leakage Contracts

Overview

Leakage contracts are a security abstraction introduced at the Instruction Set Architecture (ISA) level to formally specify the side-channel leakage behavior of processors. They capture the information a processor may leak via microarchitectural side channels, serving as a single source of truth for verifying both hardware compliance and software security. By decoupling hardware and software verification through a shared contract, they enable modular analysis: any program verified against a contract can run safely on any processor verified against the same contract.

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

2 connections

Genoa ← implements 87% 1e

Genoa is used to write leakage contracts per prior work.

leak ← implements 90% 1e

Defines how contracts emit and accumulate leakages.

LINKED ENTITIES

2 links

Genoa IMPLEMENTS Extracted graph relationship

leak IMPLEMENTS Extracted graph relationship

CITATIONS

9 sources

9 citations — click to expand

[1] Leakage contracts specify both functional behavior and leakage behavior of processors, with value storage split into ISA state σ and accumulated leakage λ. Leakage Contracts for Processors with Transitions and Glitches

[2] Hardware verification checks that every observable leak in hardware has a corresponding leak emitted by the contract, expressed as an SMT problem with bitvector theories. Leakage Contracts for Processors with Transitions and Glitches

[3] Software verification records all leakages emitted by the contract during program execution and proves order-t probing security using Fourier coefficient approximation. Leakage Contracts for Processors with Transitions and Glitches

[4] Genoa is a DSL introduced by Bloem et al. for specifying leakage contracts; scVerif is used to verify software against contracts via manual translation. Leakage Contracts for Processors with Transitions and Glitches

[5] The Ibex contract maintains architectural registers (pc, next_pc, regs) and leakage registers (prev_regs, mem_last_addr, mem_last_read, prev_rd, prev_rs1, prev_rs2). Leakage Contracts for Processors with Transitions and Glitches

[6] Glitches in Ibex arise from register file read port logic (one-hot decoder with AND/OR gates) and can propagate to write ports in worst case. Leakage Contracts for Processors with Transitions and Glitches

[7] LeaSyn is a tool that automatically synthesizes sound and precise leakage contracts for RTL processor designs from user-provided templates. Synthesis of Sound and Precise Leakage Contracts for Open-Source RISC-V Processors

[8] A semi-automatic methodology synthesizes hardware-software leakage contracts for RISC-V using human-defined templates and automated test-case generation. Synthesizing Hardware-Software Leakage Contracts for RISC-V Open-Source Processors

[9] The extended gate-level leakage model formalizes signal stability and detectable difference per gate type, reducing false positives from glitch propagation. Leakage Contracts for Processors with Transitions and Glitches