Randomized Instruction Stream Generation
TechniqueRandomized instruction stream generation is a classical verification technique in which processor test stimuli are produced by randomly creating instruction words that are then executed and compared against a reference model (typically an instruction set simulator, ISS). It is widely used as a baseline for functional processor verification, but suffers from limited effectiveness on corner cases because random streams rarely exercise deep or rarely-taken control paths. Subsequent work has therefore extended it with model-based constraint solving, coverage-guided fuzzing, and coverage-guided aging to systematically push randomized streams toward unexplored processor behavior.
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Randomized Instruction Stream Generation
Definition
Randomized instruction stream generation is a processor-level stimuli generation technique in which binary instruction words are produced at random and fed to the design under verification (DUT). The DUT's resulting architectural state (typically register and memory values) is then compared against a reference model, most commonly an instruction set simulator (ISS) of the same instruction set architecture. It is described in the processor verification literature as the classical approach to test program generation, against which more directed methods are measured.
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