Overview

Processor-level input stimuli generation is the generation of instruction-level test inputs used to verify processor designs. In simulation-based processor verification, these stimuli are intended to exercise processor behavior thoroughly enough to expose mismatches or bugs in the implementation.

Bruns et al. describe this area as a long-standing part of simulation-based processor verification, with multiple families of approaches proposed to improve the generation of processor-level stimuli. Reported directions include model-based test generators driven by input-format specifications, constraint-based generation using CSP/SMT solvers, optimizations for propagating constraints across multiple instructions, mining processor manuals to obtain input models, coverage-guided generation based on Bayesian networks, other machine-learning-based methods, and symbolic-execution-based formal techniques.