Technique
Technique
491 entities#
1 Coverage-Guided Fuzzing
34 2 hardware fuzzing
26 3 Formal Verification
25 4 CSR-transition coverage
24 5 Co-Simulation
23 6 Simulation-Based Verification
20 7 RTL simulation
20 8 Mutation-Based Fuzzing
17 9 Direct Instruction Injection
16 10 random instruction generation
15 11 differential testing
15 12 Constraint Solving
13 13 Coverage-Driven Verification
13 14 register coverage
12 15 Differential Fuzzing
12 16 ISA simulation
12 17 Tandem Simulation
11 18 Object-Oriented Stimulus Generation
11 19 Runtime Instruction Morphing
11 20 Synchronizable Co-simulation
11 21 constrained random verification
11 22 constrained-random test generation
11 23 Model-Based Test Generation
10 24 on-the-fly instruction stream generation
9 25 Interval Property Checking
9 26 Constraint Programming
9 27 Dynamic Swappable Memory
9 28 Automatic Property Generation
9 29 Constrained-Random Verification (CRV)
9 30 Processor Fuzzing
9 31 Multi-Armed Bandit (MAB)
8 32 Fuzzing
8 33 Squash (order-decoupled fusion)
8 34 Counterexample Shrinking
8 35 Instruction Scheduling
8 36 Differential Information Flow Tracking
8 37 Constrained-Random Stimulus Generation
8 38 Batch (tight packing of verification events)
8 39 Random Test Program Generation
7 40 CPU fuzzing
7 41 Test Case Shrinking
7 42 Symbolic Execution
7 43 Replay (lightweight debugging by event retransmission)
7 44 Top-Down Stimulus Planning
7 45 Register-Coverage Guided Fuzzing
7 46 transformer language model for instruction sequences
7 47 Stimulus Template
7 48 Multicore Parallelization
7 49 constraint-based test generation
7 50 Reinforcement Learning
7 51 Coverage-based Greybox Fuzzing
7 52 Coverage-guided Aging
7 53 Model-based Stimuli Generation
7 54 Architecture Description
7 55 Bounded Model Checking
7 56 Burch-Dill Correspondence Checking
7 57 Asymmetric ISA Pre-Simulation
6 58 Generic Simulation Method
6 59 Ant Colony Optimization
6 60 Randomized Instruction Generation
6 61 Instruction Morphing
6 62 Statistical Fault Injection (SFI)
6 63 RTL Fuzzing
6 64 Cross-Level Testing
6 65 ISS Code Generation
6 66 Mapping Functions
6 67 Hardware-Software Co-Verification
6 68 Register Allocation
6 69 Directed Test
6 70 Pipeline Modeling
6 71 REVERSI
6 72 Just-in-Time Compiled Simulation
6 73 Dependency Analysis
6 74 Instruction Stream Generation
6 75 static analysis
5 76 multiplexer toggle coverage
5 77 Functional Verification
5 78 satisfiability modulo theories
5 79 instruction fuzzing
5 80 Translation Buffer
5 81 Automated Design Inspection
5 82 Intermediate Program Construction
5 83 Constraint Satisfaction Problem Solving
5 84 Directed-Random Test Generation
5 85 reference model comparison
5 86 communicating extended finite state machines
5 87 Design-for-Test (DfT)
5 88 Code Generation
5 89 AI-Driven Test Generation
5 90 Directed-Random Test Sequence Generation
5 91 Constraint-Based Randomization
5 92 CPU-assisted test-case generation
5 93 Maintaining Arc Consistency
5 94 Directed-Random Stimulus
5 95 Hardware-based Seed Selection
5 96 Golden Reference Model Comparison
5 97 Training Derivation Strategy
5 98 code-based test generation
4 99 congestor
4 100 CI/CD pipeline
4 100 of 491 shown
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