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STIMSMITH
Technique

Technique

1259 entities
#
1
Coverage-Guided Fuzzing
83
2
differential testing
79
3
hardware fuzzing
67
4
Fuzzing
60
5
Formal Verification
56
6
Symbolic Execution
51
7
Co-Simulation
36
8
RTL simulation
31
9
Mutation-Based Fuzzing
30
10
constrained random verification
30
11
constrained-random test generation
29
12
Simulation-Based Verification
27
13
CSR-transition coverage
27
14
random instruction generation
26
15
Processor Fuzzing
23
16
Coverage-Driven Verification
23
17
CPU fuzzing
21
18
Reinforcement Learning
20
19
Grey-Box Fuzzing
20
20
Hardware-Guided Reinforcement Learning
20
21
Model Checking
19
22
Constrained-Random Stimulus Generation
18
23
Asymmetric ISA Pre-Simulation
18
24
Differential Fuzzing
18
25
Direct Instruction Injection
17
26
Directed Testing
16
27
Constrained-Random Verification (CRV)
16
28
Model-Based Test Generation
15
29
FLAME
15
30
register coverage
15
31
Bounded Model Checking
15
32
Constraint Solving
15
33
Program Reduction
14
34
RTL Fuzzing
14
35
White-Box Fuzzing
14
36
UVM (Universal Verification Methodology)
14
37
Coverage-based Greybox Fuzzing
14
38
Fuzz Testing
14
39
Bounded Model Checking (BMC)
13
40
Control Flow Entanglement with Data Flow
13
41
Concolic Testing
13
42
Runtime Instruction Morphing
13
43
Contradiction Analysis
12
44
Constraint Programming
12
45
ISA simulation
12
46
Covariance Matrix Adaptation Evolution Strategy
12
47
Mutation Testing
12
48
coverage-directed test generation
12
49
Guided Test Case Generation
12
50
UniGen2
11
51
Property Checking
11
52
Proximal Policy Optimization
11
53
Object-Oriented Stimulus Generation
11
54
Synchronizable Co-simulation
11
55
Tandem Simulation
11
56
Intermediate Program Construction
11
57
LLM-based Test Generation
11
58
Hash-based Differential Fault Effect Equivalence Check (CDIF+FEEC)
11
59
Instruction Stream Generation
11
60
constrained-random instruction generation
11
61
Functional Coverage
11
62
Maximal Convex Subgraph Enumeration
11
63
Constrained Random Testing
10
64
Transformer Language Model
10
65
Constraint-Based Randomization
10
66
UVM
10
67
Translation Buffer
10
68
Coverage-guided Aging
10
69
Universal Verification Methodology
10
70
Automatic Property Generation
9
71
software fuzzing
9
72
Contention-guided Hardware Fuzzing
9
73
Equivalence Checking
9
74
Contextual Bandit
9
75
Black-Box Fuzzing
9
76
Directed-Random Test Generation
9
77
litmus tests
9
78
Mutation-Based Testing
9
79
Interval Property Checking
9
80
Dynamic Swappable Memory
9
81
on-the-fly instruction stream generation
9
82
Mutation-Analysis-Guided Fuzzing
9
83
Theorem Proving
9
84
Hindley-Milner Type Inference
9
85
LLM-based Test Code Generation
9
86
instruction sequence generation
8
87
Statistical Fault Injection (SFI)
8
88
Uniform Generation of SAT Witnesses
8
89
GRPO with State Mutation
8
90
Register-Coverage Guided Fuzzing
8
91
Execution Controller
8
92
Random Test Program Generation
8
93
Directed Fuzzing
8
94
Emulation
8
95
Instruction Scheduling
8
96
Counterexample Shrinking
8
97
test program generation
8
98
Coverage-Guided Test Generation
8
99
Batch (tight packing of verification events)
8
100
Squash (order-decoupled fusion)
8
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