Technique
Technique
491 entities#
1 Hardware-Based Mutation
3 2 Interruption and Exception Simulation
3 3 Parallelized Fork
3 4 On-the-Fly Instruction Stream Evolution
3 5 Pre-Silicon Verification
3 6 Class-Based Testbench
3 7 Theorem Proving
3 8 Assertion-Based Verification
3 9 Machine Learning for Fuzzing
3 10 Dynamic Redundant Load Pruning
3 11 Data Path Modeling
3 12 Concolic Testing
3 13 Completeness Analysis
3 14 Seed Corpus Optimization
3 15 Instruction Injection
3 16 Dependency-Aware Heuristic
3 17 Frequency Heuristic
3 18 Differential Fuzz Testing
3 19 Execution Controller
3 20 Model Checking
3 21 Randomized Instruction Stream Generation
3 22 RTL Flattening
3 23 hierarchical constrained-random stimulus generation
3 24 Property Checking
3 25 RTL Co-simulation
3 26 RVFI-DII
3 27 DPI Interface
3 28 Specification-based Test Generation
3 29 path enumeration
3 30 template-based test generation
3 31 Hardware-Based Mutation Strategy
3 32 Fuzz Testing
3 33 functional coverage measurement
3 34 Biased Pseudorandom Dynamic Generation
2 35 mispredicted path fuzzing
2 36 Register Value Comparison
2 37 Fast Exploration Mutation
2 38 Bitflip Mutation
2 39 TLM Fifo Asynchronous Communication
2 40 VIP Level Parallelism
2 41 Asynchronous Worker Threads
2 42 Lazy Merging of Directed Streams
2 43 Profiling
2 44 BDD-based Constraint Solving
2 45 hardware prototyping
2 46 Transaction Level Modeling
2 47 Discrete Event Simulation
2 48 Inter-Process Communication
2 49 user-assisted code generation
2 50 Object-Oriented Constraint Partitioning
2 51 Maintain-Arc-Consistency
2 52 Constraint-Based Branch Stimulus Generation
2 53 pseudorandom generator (PRG)
2 54 stimulus generation
2 55 recurrent neural network-based constraint alteration
2 56 Pseudorandom Generator (PRG) Stimulus Generation
2 57 Hardware-based Mutation Strategies
2 58 blacklisting instructions
2 59 Directed Random Stimuli Generation
2 60 Simulation-based Processor Verification
2 61 Symbolic Execution for Test Generation
2 62 Endless Instruction Stream Generation
2 63 Post-processing Test Vector Clustering
2 64 Dynamic Program Analysis
2 65 Object-Oriented Verification
2 66 coverage-directed test generation
2 67 Dedicated DFI Cache
2 68 instruction field mutation
2 69 post-processing trace analysis
2 70 opcode injection
2 71 Virtual Coverage
2 72 object-oriented constraint-based instruction generation
2 73 Bottom-Up Implementation
2 74 instruction sequence generation
2 75 Coverage-Directed Test Selection
2 76 Supervised Learning
2 77 Counterexample-Driven Development
2 78 Sequence Import/Export
2 79 labeling phase
2 80 dependency annotation
2 81 positive and negative testing
2 82 Coverage-guided Aging Counter
2 83 Randomized Test Strategy
2 84 Cross-product Coverage Points
2 85 Automated Test Case Reduction
2 86 Model-Based Random Testing
2 87 context-free grammar specification with annotations
2 88 single-instruction isolation
2 89 overlapping template composition
2 90 Constraint Logic Programming
2 91 automated translation from architecture specifications
2 92 Emulation
2 93 Transaction Abstraction
2 94 Branch Scenario Constraint Modeling
2 95 Static Test Suite Generation
2 96 Fault Injection
2 97 Fuzzing-Based Test Generation
2 98 Randomized Instruction Sequence Generation
2 99 Scan-Based DfT with ATPG
2 100 Symbolic Execution Co-Simulation
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