blacklisting instructions
TechniqueBlacklisting instructions is a verification technique in which selected instructions are temporarily excluded from generated tests so that functional regressions can run while design modules or instruction support are still incomplete. In the cited RISC-V vector accelerator verification environment, many instructions were initially blacklisted and then gradually re-enabled as errors were fixed and missing features were implemented.
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Overview
blacklisting instructions is a staged verification technique used to keep generated tests functional when parts of a design are still under development. In the cited RISC-V vector accelerator verification environment, the verification team initially blacklisted many instructions from generated tests because some design modules were still in development for much of the verification process. This allowed functional tests to run at each iteration instead of being dominated by known unsupported or incomplete instruction behavior.
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