Register Value Comparison

Technique

Register Value Comparison is a processor-verification technique that compares architectural register states between processor implementations, such as an instruction set simulator and an RTL core, to detect functional mismatches. The evidence describes using register changes as synchronization and comparison points to reduce false mismatches and avoid unnecessary performance overhead.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Register Value Comparison is a technique for checking whether two processor implementations exhibit the same behavior by comparing their register values. In the cited cross-level processor-verification setting, this comparison is used to determine whether the behavior of processor cores is equal; unequal register values indicate a mismatch. [C1]

Verification role

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LINKED ENTITIES

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Co-simulation USED_IN Extracted graph relationship

CITATIONS

7 sources

7 citations — click to expand

[1] C1: Register Value Comparison checks whether processor behaviors are equal by comparing register values, and unequal values indicate a mismatch. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] C2: Important processor functionality can lead to register value changes, making register comparison useful for detecting functional mismatches. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] C3: Comparing an ISS with a pipelined RTL core is challenging because a pipelined core may lack a general complete-instruction signal. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] C4: Register values should be compared or logged right after the respective instruction completes, and synchronization is needed to avoid false mismatches. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] C5: Register comparison should only be executed when a register value changes, because frequent comparisons degrade performance and some instructions such as writes to x0 do not change register values. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] C6: The Execution Controller detects a register value change, compares ISS and RTL-core registers, reports mismatches, and stops the simulation in the described example. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[7] C7: The evidence describes a verification flow comparing an ISS and RTL core, supporting the provided relationship that Register Value Comparison is used in Co-Simulation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing