Overview

Register Value Comparison is a technique for checking whether two processor implementations exhibit the same behavior by comparing their register values. In the cited cross-level processor-verification setting, this comparison is used to determine whether the behavior of processor cores is equal; unequal register values indicate a mismatch. [C1]

Verification role

The technique is motivated by the observation that important processor functionality eventually causes a register value change. For example, an add x1, x2, x3 instruction reads registers x2 and x3, computes a result, and writes it to x1; therefore, comparing register values can expose functional mismatches between implementations. [C2]

This is especially relevant when comparing an instruction set simulator (ISS) with a pipelined RTL core. The evidence notes that such comparison is challenging because the implementations are different, and a pipelined RTL processor may not provide a general signal indicating that an instruction has completed. [C3]

Synchronization point

Register values should be compared, or logged, immediately after the corresponding instruction has completed on the processor cores. Without instruction-execution synchronization, many false mismatches can be reported. [C4]

To reduce unnecessary work, the comparison should be performed only when a register value has actually changed. The evidence states that comparing too frequently causes performance degradation, and gives the example of add x0, x2, x3, where no architectural register value changes because x0 always remains zero. [C5]

Error detection behavior

In the described execution-controller flow, register value changes are used as synchronization and comparison points. When a register value change is detected, the controller compares the registers of the ISS and the RTL core. In the example, the RTL core erroneously executes an LWU x8, x0, 48 instruction, causing a change in x8; the comparison discovers mismatches between x8 and x6, raises an error, and stops the simulation. [C6]

Used in co-simulation

The provided relationship classifies Register Value Comparison as used in Co-Simulation. The evidence supports the underlying co-execution scenario by describing comparison between an ISS and an RTL core executing corresponding instruction streams. [C7]