Post-processing Test Vector Clustering

Technique

Post-processing Test Vector Clustering is an automatic reduction step used after coverage-guided fuzzing in a cross-level processor verification flow. It groups test vectors that trigger mismatches and appear to expose the same bug, representing each cluster by a unique test vector, and relies on a logging-oriented co-simulation build to identify the instruction associated with the bug.

First seen 5/26/2026

Last seen 5/29/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Post-processing Test Vector Clustering is a technique used after a coverage-guided fuzzing loop in a cross-level processor verification workflow. In the described flow, fuzzing first generates test vectors for co-simulation of an RTL processor core and a reference instruction set simulator (ISS); post-processing then reduces the generated set of mismatch-triggering test vectors. [C1]

The purpose of the technique is to reduce manual analysis effort for verification engineers by clustering test vectors that trigger mismatches and encapsulating vectors that detect the same bug. [C2]

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RELATIONSHIPS

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Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← introduces 100% 3e

The paper introduces post-processing test vector clustering to group test vectors that reveal the same bug.

LINKED ENTITIES

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Coverage-Guided Fuzzing preceded_by The evidence describes the overall approach as two subsequent steps: a coverage-guided fuzzing loop followed by post-processing to reduce the generated set.

Co-Simulation uses The evidence states that post-processing uses a custom co-simulation version with logging instrumentation to provide feedback for clustering.

CITATIONS

7 sources

7 citations — click to expand

[1] C1: The verification flow consists of a coverage-guided fuzzing loop that generates test vectors followed by post-processing that reduces the generated set; the loop uses co-simulation of an RTL core and reference ISS, and mismatches are detected through register-value comparison. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] C2: The post-processing step clusters test vectors that trigger mismatches in order to reduce manual labor and encapsulate vectors that detect the same bug, using co-simulation compiled with more extensive logging instrumentation. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] C3: Fuzzing can generate many test vectors, reach high coverage, and uncover numerous bugs, but many test vectors may reveal the same bug, motivating clustering to save manual analysis time. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] C4: Each cluster is represented by a unique test vector that behaves like every other test vector in the cluster. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[5] C5: The post-processing co-simulation logs all executed instructions with corresponding addresses and uses additional logging feedback for clustering. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[6] C6: The logging-enabled post-processing co-simulation is slower due to hard-disk write accesses and does not need the coverage instrumentation that is essential for fuzzing. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[7] C7: The post-processing extracts the instruction that leads to the bug and distinguishes mismatches in two cases, though the provided evidence does not specify those cases. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing