Symbolic Execution for Test Generation

Technique

Symbolic execution for test generation is referenced in processor-verification literature as a formal-methods-based way to generate test cases, including at the instruction set simulator (ISS) level. In the cited RISC-V verification context, it is positioned alongside other simulation-based and formal approaches, and contrasted with coverage-guided fuzzing approaches for cross-level processor verification.

First seen 5/28/2026

Last seen 5/28/2026

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Overview

Symbolic Execution for Test Generation is discussed in the processor-verification literature as a formal-methods-based technique used to generate test cases. In the cited evidence, symbolic execution is specifically mentioned as having been used for test-case generation at the instruction set simulator (ISS) level. [c1]

Role in processor verification

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RELATIONSHIPS

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Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing ← compares with 75% 1e

The paper mentions symbolic execution as a related test generation technique.

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Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing COMPARES_WITH Extracted graph relationship

CITATIONS

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4 citations — click to collapse

[1] Symbolic-execution-based formal methods have been used for test-case generation at the ISS level. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[2] Processor-verification test generation literature includes model-based generators, CSP/SMT-based constraint approaches, coverage-guided generation using Bayesian networks or other machine-learning techniques, and fuzzing-based approaches. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[3] The coverage-guided fuzzing paper proposes a co-simulation setup that feeds the same instruction sequences to a reference ISS and a processor core under test, supports arbitrary instruction sequences, and generates test cases one after another. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing

[4] The cited paper notes that formal techniques may be susceptible to scalability issues in the RISC-V verification context. Efficient Cross-Level Processor Verification using Coverage-guided Fuzzing