Profiling

Technique

Profiling is a performance-optimization technique used to identify execution-time bottlenecks. In the RISCV-DV testbench optimization case study, profiling narrowed more than 15,000 lines of code to about 200 repeatedly executed lines that were key to generator performance, and it helped identify four major bottlenecks.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 2 chunks

Wiki v1

WIKI

Overview

Profiling is presented as the most important step in performance optimization for the RISCV-DV generator case study. The codebase contained more than 15,000 lines of code, and profiling reduced the optimization focus to roughly 200 repeatedly executed lines that were key to generator performance. [C1]

Purpose

READ FULL ARTICLE →

NEIGHBORHOOD

No graph connections found for this entity yet. It may appear in future ingestion runs.

explore full graph →

RELATIONSHIPS

1 connections

riscv-dv ← uses 95% 1e

Profiling was used to identify bottlenecks in the RISCV-DV generator.

CITATIONS

8 sources

8 citations — click to expand

[1] Profiling was presented as the most important performance-optimization step and reduced the RISCV-DV focus from more than 15,000 lines to about 200 repeatedly executed performance-critical lines. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[2] Profiling results, combined with algorithmic-complexity analysis, identified four major RISCV-DV generator bottlenecks and ranked them by impact. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[3] uvm_trace is described as an eUVM construct that helps formally identify testbench bottlenecks at macro level. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[4] gprof is identified as an open-source tool useful for micro-level profiling. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[5] The example uvm_trace instrumentation surrounds an instruction-randomization loop, and UVM_TRACE log messages include wall-clock timestamps taken at trace invocation. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[6] The profiling setup used riscv_instr_base_test with seven directed streams because RISCV-DV execution time varies significantly with selected parameters. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[7] The first two bottlenecks were linear constraint-solving workloads suited to multicore parallelization; the fourth was affected by memory allocation; and the third reflected sub-optimal algorithmic implementation requiring architectural change. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings

[8] Each uvm_trace invocation performs an operating-system call to fetch the current clock time, so reckless use can increase testbench runtime significantly. [PDF] Crafting a Million Instructions/Sec RISCV-DV - DVCon Proceedings