Technique
Technique
1157 entities#
1 event fusion
4 2 functional coverage closure
4 3 SystemVerilog Assertions (SVA)
4 4 Dynamic Fault Collapsing (DFC)
4 5 Register Coverage Metric
4 6 Differential Checking
4 7 abstract constraint satisfaction problem
4 8 abstraction refinement
4 9 Fault Effect Equivalence Check (FEEC)
4 10 Combinatorial Generation
4 11 Hardware-Accelerated RTL Simulation
4 12 Instruction Selection
4 13 Random Generation
4 14 Model-Based Generation
4 15 Prompt Engineering
4 16 Boolean Satisfiability (SAT)
4 17 Iterative Stimuli Generation
4 18 Smart Shrinking
4 19 Naive Stimuli Generation
4 20 Ternary Simulation
4 21 Coverage-Conditioned Training
4 22 Generative Model-Based Processor Fuzzing
4 23 Feedback-Based Verification
4 24 Static Single Assignment Form
4 25 Reachability Analysis
4 26 Assembly Synthesis
4 27 Abstract Syntax Tree Generation
4 28 Wave Dynamic Differential Logic
4 29 Coverage-Driven Instruction Generation
4 30 test plan generation
4 31 directed semantic tests
4 32 supervised fine-tuning
4 33 Deep Q-Learning
4 34 Search Tree with Constraint Propagation
4 35 Masking
4 36 random test-case generation
4 37 Out-of-Order Execution
4 38 Side Channel Analysis
4 39 Coverage-Guided Mutation-Based Fuzzing
4 40 Constant Time Execution Analysis
4 41 Parameterised Invariants
4 42 GenerateSolution algorithm
4 43 Random Sequence Generation
4 44 Model-Based Test Program Generation
4 45 Constraint-Based Random Generation
4 46 Recurrent Neural Network (RNN)
4 47 Control Flow Over-Tainting Mitigation
4 48 Binary Decision Diagrams
4 49 Data Assignment
4 50 Modulo Scheduling
4 51 CI/CD pipeline
4 52 counter-based node monitoring
4 53 Consistency Assertions
4 54 Basic Block Coverage Tracing
4 55 TCG-based Instrumentation
4 56 functional test program generation
4 57 Bottom-Up Instruction Space Exploration
4 58 State Prioritization
4 59 Differential CPU Fuzzing
4 60 grammar-based ISG
4 61 Taint Liveness Annotation
3 62 symbolic solver
3 63 State Decomposition
3 64 Taint Coverage Matrix
3 65 Hardware Dynamic Information Flow Tracking
3 66 Clausal Reduction Optimization
3 67 Interrupt and Exception Injection
3 68 VACO
3 69 Difftest
3 70 whitebox testing
3 71 On-the-Fly Instruction Stream Evolution
3 72 Hardware-Based Mutation Strategy
3 73 path enumeration
3 74 Lockstep Co-Simulation Methodology
3 75 PPO
3 76 Bi-LSTM
3 77 Transformer architecture
3 78 Tandem Execution
3 79 RTL Co-simulation
3 80 Single-Class Randomization Architecture
3 81 Parallelized Fork
3 82 Dual-Pass Branch Generation
3 83 Coverage-Guided Hardware-Software Contract Fuzzing
3 84 coverage score prediction
3 85 Off-Platform Floating-Point Operand Pre-Generation
3 86 Concurrent Multi-Threaded Test-Case Generation
3 87 FPGA acceleration
3 88 hierarchical constrained-random stimulus generation
3 89 Simulation-based Functional Verification
3 90 cross-entropy loss for sequence generation
3 91 Compiled Simulation
3 92 sequential modeling task for test generation
3 93 Directed Instruction Stream Generation
3 94 Coverage-Guided Property Testing
3 95 Multi-Pass Consistency Checking
3 96 design simulation
3 97 GenRandNum procedure
3 98 ApproxMC
3 99 RVFI-DII
3 100 Instruction Injection
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