Technique
Technique
491 entities#
1 Ridge Regression
2 2 Principal Component Analysis (PCA)
2 3 KMeans Clustering
2 4 RISC-V Instruction Tokenization
2 5 ISS-RTL Co-Simulation
2 6 FPGA-Assisted RTL Verification
2 7 prologue and epilogue instruction insertion
2 8 Static Formal Verification
2 9 Instruction Legality Checking
2 10 backward symbolic execution
2 11 multi-level packing strategy
2 12 Coverage-Guided Test Generation
2 13 Cross-Level Verification
2 14 Syntax-Guided Synthesis
2 15 model checking based test generation
2 16 Randomized Test Generation
2 17 Reorder Buffer Monitoring
2 18 shift template composition
2 19 concatenation template composition
2 20 Logic Fuzzer Enhanced Co-simulation
2 21 RTL Symbolization
2 22 Branch Coverage Instrumentation
2 23 Roulette Wheel Selection
2 24 k-induction
2 25 SAT-based Formal Verification
2 26 Pseudo-Random Stimulus Generation
2 27 Pipelined Execution
2 28 pipeline interaction coverage
2 29 Backward Data-Flow Analysis
2 30 multi-head self-attention
2 31 static formal analysis
2 32 gradient-based sequence update
2 33 ISA syntax correction
2 34 post-silicon fuzzing
2 35 Polynomial Formal Verification
2 36 FPGA Prototyping
2 37 Direct Test Generation
2 38 Mutation-Based Test Generation
2 39 Genetic Algorithm Test Generation
2 40 Proximal Policy Optimization
2 41 Directed Testing
2 42 Deep Reinforcement Learning
2 43 counter-example guided synthesis
1 44 template placement algorithm
1 45 arc consistency
1 46 constraint solving for test generation
1 47 FSM traversal based test generation
1 48 Counterexample Reduction
1 49 Trace-Based Verification
1 50 Memory Concurrency Testing
1 51 Difference-based Testing
1 52 feedback-guided fuzzing
1 53 HCL Control Logic Description
1 54 DPI-based Synchronization
1 55 custom tracer for execution log capture
1 56 LLM Fine-tuning for RTL
1 57 Pipeline Flushing
1 58 custom instruction verification
1 59 LLM-aided FPGA Parallelism
1 60 Havoc Mutation
1 61 Lowered VIAM
1 62 C-Code Generation
1 63 BDD solving for constraint randomization
1 64 sequential randomization of instruction fields
1 65 Array Constraints with foreach Construct
1 66 hazard handling
1 67 Random Instruction Stream
1 68 Instruction Generation
1 69 Bayesian Network-based Coverage-Directed Test Generation
1 70 Automatic Verification
1 71 pseudo-random test-program generation
1 72 Custom UVM Factory
1 73 Burch-Dill Verification Method
1 74 Bounded Model Checking (BMC)
1 75 Single Static Assignment (SSA)
1 76 Boolean Satisfiability Checking
1 77 Symbolic QED
1 78 SystemVerilog foreach Array Constraints
1 79 Context Switching Optimization
1 80 Feedback-Driven Generation
1 81 Hybrid Fuzzer Integration
1 82 bayesian network coverage-guided test generation
1 83 simulation acceleration
1 84 Recurrent Neural Network Stimulus Generation
1 85 Randomized Testing
1 86 FPGA Parallelism
1 87 LLM-aided Stimulus Generation
1 88 SystemVerilog Random Sequence Generator
1 89 Cryptographic Seed Initialization
1 90 Instruction Set Simulator Generation
1 91 Arithmetic Mutation
1 92 Bayesian Network Test Generation
1 93 Stimulus Serialization
1 94 Constraint Satisfaction Problem-based Test Generation
1 95 Bayesian Network Coverage-Directed Test Generation
1 96 Sequential Randomization
1 97 Forward Branch Probability Enhancement
1 98 sliding mutation engine
1 99 Backward Branch Loop Control
1 100 Subgraph Isomorphism
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