HCL Control Logic Description

Technique

HCL is described in the provided evidence as a simple language for describing control logic. It is used to specify the detailed functionality of control-logic blocks in Y86-64 microprocessor designs such as the sequential SEQ design and related pipelined PIPE designs.

First seen 5/25/2026

Last seen 5/25/2026

Evidence 1 chunks

Wiki v1

WIKI

Overview

HCL Control Logic Description refers to the use of HCL, described in the evidence as "a simple language for describing control logic," to specify the detailed behavior of control-logic blocks in Y86-64 microprocessor implementations.

In the SEQ hardware structure, the control logic is implemented by multiple blocks, and the evidence states that the detailed functionality of these blocks is described in HCL. The SEQ design is identified as the sequential reference version in the cited source.

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Y86-64 USED_IN Extracted graph relationship

CITATIONS

3 sources

3 citations — click to collapse

[1] HCL is a simple language for describing control logic, and it is used to describe the detailed functionality of control-logic blocks. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[2] SEQ is presented as a sequential reference version whose hardware structure includes fetch, decode, execute, memory, write-back, and PC-update behavior. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5

[3] PIPE is a five-stage pipeline implementing the Y86-64 instruction set, using similar functional blocks to SEQ plus pipeline registers and added control logic for hazards. Formal Verification of Pipelined Y86-64 Microprocessors with UCLID5